Array substrate for in-plane switching mode liquid crystal display device having double-layered metal patterns and method of fabricating the same
An array substrate of an in-plane switching liquid crystal display device includes, among other features, a gate electrode and a gate line having a first double-layered structure consisting of a first barrier layer and a first low resistance metallic layer; a data line defining a pixel region with the gate line, the data line having a second double-layered structure consisting of a second barrier layer and a second low resistance metallic layer; a plurality of common electrodes disposed in a direction opposite to an adjacent gate line; a thin film transistor (TFT) near a crossing of the gate and data lines, each of the source and drain electrodes of the TFT having the same double-layered structure as the data line; and a plurality of pixel electrodes arranged in an alternating pattern with the common electrodes and disposed in the direction opposite the adjacent gate line.
1. A method of forming an array substrate for use in an in-plane switching liquid crystal display device, comprising:
forming a gate line and a gate electrode on a substrate, the gate line being disposed in a first direction and the gate electrode extending from the gate line, wherein the gate electrode and the gate line have a first double-layered structure consisting of a first barrier layer and a first low resistance metallic layer;
forming a gate pad connected to one end of the gate line;
forming a common line substantially parallel and adjacent to the gate line;
forming a data line in a second direction, the data line defining a pixel region with the gate line, wherein the data line has a second double-layered structure consisting of a second barrier layer and a second low resistance metallic layer;
forming a data pad at one end of the data line;
forming a plurality of common electrodes in a direction perpendicular to an adjacent gate line, the common electrodes extending from the common line to the pixel region;
forming a thin film transistor near a crossing of the gate and data lines, the thin film transistor including a semiconductor layer, the gate electrode, a source electrode, and a drain electrode, wherein each of the source and drain electrodes has the same double-layered structure as the data line;
forming a plurality of pixel electrodes in the direction perpendicular to the adjacent gate lines and connected to the drain electrode, wherein the pixel electrodes are arranged in an alternating pattern with the common electrodes; and
forming another semiconductor layer extended under the data line, the data pad, and the plurality of pixel electrodes,
wherein the another semiconductor layer is a double-layered structure consisting of a first layer of pure amorphous silicon and a second layer of doped amorphous silicon on the first layer, and
wherein the first layer protrudes outside from both sides of each of the data line, the data pad and the plurality of pixel electrodes.
2. The method according to claim 1 , wherein forming the pixel electrodes and forming the data line are conducted at substantially the same time, and the pixel electrodes have the same double-layered structure as the data line, wherein forming the common electrodes, forming the common line and forming the gate line are conducted at the same time, and the common electrodes and the common line have the same double-layered structure as the gate line.
3. The method according to claim 1 , wherein forming the gate pad and forming the gate line are conducted at the same time, and the gate pad has the same double-layered structure as the gate line.
4. The method according to claim 3 , further comprising removing the first low resistance metallic layer of the gate pad so that the gate pad has a single-layered structure of the first barrier layer.
5. The method according to claim 1 , wherein forming the data pad and forming the data line are performed at the same time, and the data pad has the same double-layered structure as the data line.
6. The method according to claim 5 , further comprising removing the second low resistance metallic layer of the data pad so that the data pad has a single-layered structure of the second barrier layer.
7. The method according to claim 1 , wherein the first and second barrier layers includes a metallic material selected from a group consisting of titanium (Ti), tantalum (Ta) and tungsten (W), and the first and second low resistance metallic layer includes a material selected from a group consisting of copper (Cu), silver (Ag) and platinum (Pt).
8. The method according to claim 1 , further comprising:
forming gate and data pad terminals over the gate and data pads, respectively,
wherein the gate pad terminal contacts the gate pad, and the data pad terminal contacts the data pad.
9. The method according to claim 1 , wherein the first and second barrier layers are titanium layers each having a thickness of about 100-200 angstroms, and the first and second low resistance metallic layers are copper layers each having a thickness of about 1500-2000 angstroms.
10. The method according to claim 1 , wherein the first and second barrier layers are titanium layers each having a thickness of about 1000 angstroms, and the first and second low resistance metallic layers are copper layers each having a thickness of about 1500-2000 angstroms.
11. The method according to claim 1 , wherein forming the gate and data lines uses a mixed etching solution including hydrogen peroxide (H 2 O 2 ), an etching agent, a solution having fluoride (F), and an additive for controlling an etch profile.
12. The method according to claim 11 , wherein the etching agent includes one of SO 4 components, COOH components, and PO 4 components, wherein the SO 4 components includes one of 2KHSO 5 , KHSO 4 , and K 2 SO 4 , and wherein the COOH components is acetic acid.
13. The method according to claim 11 , wherein the solution having fluoride (F) is one of hydrogen fluoride (HF) and ammonium fluoride (NH 4 F).