IP Library Granted Patent US 8,615,062
Granted Patent B2
US 8,615,062 · App. 13/368,315 · Granted Dec 24, 2013

Adaptation using error signature analysis in a communication system

Inventor: Erik V. Chmelar (Midland, MI)
Assignee: LSI Corporation
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Quick Facts
Patent No.
US 8,615,062
App. No.
13/368,315
Granted
Dec 24, 2013
Kind
B2
Abstract

Described embodiments provide method of adapting pulse response taps of a receiver. An analog-to-digital converter (ADC) generates an ADC value for each bit sample of a received signal. An error signature analysis (ESA) module defines a window of bit samples and, for the window, estimates a bit value corresponding to each sample based on the ADC value. The ESA module generates (i) a reconstructed ADC value corresponding to an estimated cursor bit based on a number of pre-cursor estimated bits, the estimated cursor bit, and a number of post-cursor estimated bits, and (ii) an error signature value based on the reconstructed ADC value and the ADC value. Based on the error signature value and a minimum pulse response value, it is determined whether the cursor bit corresponds to residual inter-symbol interference (ISI), and, if so, the error signature value is accumulated and tap values for each pulse response tap are adapted.

Claims (114)

1. A method of adapting one or more pulse response taps of a receiver coupled to a communication channel, the method comprising:

generating, by an analog-to-digital converter (ADC) of the receiver, an actual ADC value for each bit sample of a received signal;

defining, by an error signature analysis module of the receiver, a window of bit samples, wherein, for the window:

estimating a bit value corresponding to each bit sample based on the corresponding ADC value;

generating (i) a reconstructed ADC value corresponding to an estimated cursor bit value based on a first predetermined number of pre-cursor estimated bit values, the estimated cursor bit value, and a second predetermined number of post-cursor estimated bit values, and (ii) an error signature value corresponding to each bit sample based on the reconstructed ADC value and the actual ADC value;

determining whether the cursor bit of the window corresponds to residual inter-symbol interference based on the error signature value and a minimum pulse response value; and, if so:

accumulating the error signature value to a residual inter-symbol interference accumulator; and

adapting, based on the residual inter-symbol interference accumulator value, tap values for each of the one or more pulse response taps of the receiver.

2. The method of claim 1 , wherein:

the first predetermined number corresponds to a number of pre-cursor taps of the receiver, and

the second predetermined number corresponds to a number of post-cursor taps of the receiver.

3. The method of claim 1 , further comprising:

by the error signature analysis module:

determining, when the window comprises one or more estimated bit values,

whether the cursor bit of the window is an incorrectly estimated bit value based on (i) the error signature value for the first predetermined number of pre-cursor estimated bit values, the cursor estimated bit value, and the second predetermined number of post-cursor estimated bit values, and (ii) an error threshold value.

4. The method of claim 3 , further comprising:

adapting, based on the error signature values, the error threshold value.

5. The method of claim 4 , further comprising:

determining whether the error signature value is a lone pulse;

if the error signature value is a lone pulse, (i) accumulating the error signature value, and (ii) incrementing an error snapshot counter; and

if the error snapshot counter is greater than a predetermined threshold, updating the error threshold value.

6. The method of claim 5 ,

wherein the step of determining whether an error pulse is a lone pulse comprises:

determining the error signature values of (i) a first bit, the first bit located a predetermined number of bits before the cursor bit, and (ii) a second bit, the second bit located a predetermined number of bits after the cursor bit; and

determining the error signature value is a lone pulse if the error signature values of the first bit and the second bit are less than the error signature value of the cursor bit minus the error threshold; and

wherein the step of updating the error threshold value comprises:

setting the error threshold substantially equal to a midpoint value between twice the cursor tap pulse response value and twice a first pre-cursor tap pulse response value.

7. The method of claim 6 , wherein the error threshold value is set according to the equation: vth error =h 0 +h −1 , wherein vth error is the error threshold value, h 0 is the cursor pulse response value and h −1 is the first pre-cursor pulse response value.

8. The method of claim 3 , further comprising:

if the error signature value is less than or equal to the error threshold value, determining that the bit is correctly estimated; and

otherwise, if the error signature value is greater than the error threshold value, (i) determining that the bit is incorrectly estimated, and (ii) generating a corrected bit estimate value.

9. The method of claim 8 , further comprising, if the bit is incorrectly estimated:

re-estimating the reconstructed ADC value based on the corrected bit estimate value; and

re-generating the error signature value based on the re-estimated reconstructed ADC value.

10. The method of claim 1 , wherein the step of generating a reconstructed ADC value comprises:

summing, for each tap of the system:

each estimated bit value multiplied by the corresponding pulse impulse response.

11. The method of claim 10 , wherein the reconstructed ADC value is given by the equation: a′[j]=Σ taps b′[−i+j]×h i , where a′ is the reconstructed ADC value, j is a bit index of the bit sample, b′ is the estimated bit value, i is a tap number index, and h i is the tap pulse response value.

12. The method of claim 1 , wherein the step of generating an error signature value comprises subtracting the reconstructed ADC value from the actual ADC value for each bit sample.

13. The method of claim 12 , wherein the error signature value is given by the equation: e′[j]=|a[j]−α′[j]|, where e′ is the error signature value, a is the actual ADC value, a′ is the reconstructed ADC value, and j is a bit index of the bit sample.

14. The method of claim 1 , wherein the step of determining whether the cursor bit of the window corresponds to residual inter-symbol interference comprises:

determining whether the error signature value of a current bit is greater than the error threshold;

if the error signature value of the current bit is greater than the error threshold, determining whether the error signature values of the one or more pre-cursor bits are greater than the error threshold;

if either the error value of the current bit is not greater than the error threshold, or the error signature values of the one or more pre-cursor bits are greater than the error threshold:

determining whether the error value of the current bit is less than the minimum pulse response value of the receiver, wherein the minimum pulse response corresponds to the pulse response value of a last post-cursor bit of the current bit; and

incrementing a residual inter-symbol interference counter.

15. The method of claim 14 , wherein the step of adapting tap values for each of the one or more pulse response taps of the receiver comprises:

if the residual inter-symbol interference counter is greater than a predetermined threshold:

computing an average residual inter-symbol interference value; and

updating the tap values based on the average residual inter-symbol interference value.

16. The method of claim 15 ,

wherein the step of computing the average residual inter-symbol interference value comprises dividing the accumulated residual inter-symbol interference value by the value of the residual inter-symbol interference counter; and

wherein the step of updating the tap values comprises subtracting the average residual inter-symbol interference value from each tap value.

17. The method of claim 1 , wherein the step of adapting tap values for each of the one or more pulse response taps of the receiver comprises at least one of: adapting each tap value by a predetermined step value, and (ii) adapting each tap value by one of a course step value and a fine step value based on a gear-shifting value of the error signature analysis module.

18. The method of claim 1 , wherein the communication channel is a long-reach serializer/deserializer (SERDES) communication channel.

19. A non-transitory machine-readable medium, having encoded thereon program code, wherein, when the program code is executed by a machine, the machine implements a method of adapting one or more pulse response taps of a receiver coupled to a communication channel, the method comprising:

generating, by an analog-to-digital converter (ADC) of the receiver, an actual ADC value for each bit sample of a received signal;

defining, by an error signature analysis module of the receiver, a window of bit samples, wherein, for the window:

estimating a bit value corresponding to each bit sample based on the corresponding ADC value;

generating (i) a reconstructed ADC value corresponding to an estimated cursor bit value based on a first predetermined number of pre-cursor estimated bit values, the estimated cursor bit value, and a second predetermined number of post-cursor estimated bit values, and (ii) an error signature value corresponding to each bit sample based on the reconstructed ADC value and the actual ADC value;

determining whether the cursor bit of the window corresponds to residual inter-symbol interference based on the error signature value and a minimum pulse response value; and, if so:

accumulating the error signature value to a residual inter-symbol interference accumulator; and

adapting, based on the residual inter-symbol interference accumulator value, tap values for each of the one or more pulse response taps of the receiver.

20. A communication system comprising:

a transmitting device configured to transmit a signal over a communication channel to a receiver of the communication system;

an analog-to-digital converter (ADC) of the receiver configured to generate an actual ADC value for each bit sample of the signal;

an error signature analysis module of the receiver configured to define a window of bit samples, wherein, for the window, the error signature analysis module is configured to:

estimate a bit value corresponding to each bit sample based on the corresponding ADC value;

generate (i) a reconstructed ADC value corresponding to an estimated cursor bit value based on a first predetermined number of pre-cursor estimated bit values, the estimated cursor bit value, and a second predetermined number of post-cursor estimated bit values, and (ii) an error signature value corresponding to each bit sample based on the reconstructed ADC value and the actual ADC value;

determine whether the cursor bit of the window corresponds to residual inter-symbol interference based on the error signature value and a minimum pulse response value; and, if so:

accumulate the error signature value to a residual inter-symbol interference accumulator; and

adapting, based on the residual inter-symbol interference accumulator value, tap values for each of the one or more pulse response taps of the receiver.

21. A receiver for decoding received data from a communication channel, the receiver comprising:

an analog-to-digital converter (ADC) of the receiver configured to generate an actual ADC value for each bit sample of the signal;

an error signature analysis module of the receiver configured to define a window of bit samples, wherein, for the window, the error signature analysis module is configured to:

estimate a bit value corresponding to each bit sample based on the corresponding ADC value;

generate (i) a reconstructed ADC value corresponding to an estimated cursor bit value based on a first predetermined number of pre-cursor estimated bit values, the estimated cursor bit value, and a second predetermined number of post-cursor estimated bit values, and (ii) an error signature value corresponding to each bit sample based on the reconstructed ADC value and the actual ADC value;

determine whether the cursor bit of the window corresponds to residual inter-symbol interference based on the error signature value and a minimum pulse response value; and, if so:

accumulate the error signature value to a residual inter-symbol interference accumulator; and

adapting, based on the residual inter-symbol interference accumulator value, tap values for each of the one or more pulse response taps of the receiver.

22. The receiver of claim 21 , wherein:

the first predetermined number corresponds to a number of pre-cursor taps of the receiver, and

the second predetermined number corresponds to a number of post-cursor taps of the receiver.

23. The receiver of claim 21 , wherein the error signature analysis module is further configured to:

determine, when the window comprises one or more estimated bit values, whether the cursor bit of the window is an incorrectly estimated bit value based on (i) the error signature value for the first predetermined number of pre-cursor estimated bit values, the cursor estimated bit value, and the second predetermined number of post-cursor estimated bit values, and (ii) an error threshold value; and

adapt, based on the error signature values, the error threshold value.

24. The receiver of claim 23 , wherein the error signature analysis module is further configured to:

determine whether the error signature value is a lone pulse;

if the error signature value is a lone pulse, (i) accumulate the error signature value, and (ii) increment an error snapshot counter; and

if the error snapshot counter is greater than a predetermined threshold, update the error threshold value.

25. The receiver of claim 24 , wherein the error signature analysis module is configured to:

determine the error signature values of (i) a first bit, the first bit located a predetermined number of bits before the cursor bit, and (ii) a second bit, the second bit located a predetermined number of bits after the cursor bit;

determine the error signature value is a lone pulse if the error signature values of the first bit and the second bit are less than the error signature value of the cursor bit minus the error threshold; and

set the error threshold substantially equal to a midpoint value between twice the cursor tap pulse response value and twice a first pre-cursor tap pulse response value,

wherein the error threshold value is set according to the equation: vth error =h 0 +h −1 , where vth error is the error threshold value, h 0 is the cursor pulse response value and h −1 is the first pre-cursor pulse response value.

26. The receiver of claim 22 , wherein the error signature analysis module is further configured to:

if the error signature value is less than or equal to the error threshold value, determine that the bit is correctly estimated; and

otherwise, if the error signature value is greater than the error threshold value, (i) determine that the bit is incorrectly estimated, and (ii) generate a corrected bit estimate value.

27. The receiver of claim 21 , wherein the error signature analysis module is further configured to:

sum, for each tap of the system, each estimated bit value multiplied by the corresponding pulse impulse response,

wherein the reconstructed ADC value is given by the equation: a′[j]=Σ taps b′[−i+j]×h i , where a′ is the reconstructed ADC value, j is a bit index of the bit sample, b′ is the estimated bit value, i is a tap number index, and h i is the tap pulse response value.

28. The receiver of claim 21 , wherein the error signature analysis module is further configured to:

generate an error signature value by the equation: e′[j]=|a[j]−a′[j]|, where e′ is the error signature value, a is the actual ADC value, a′ is the reconstructed ADC value, and j is a bit index of the bit sample.

29. The receiver of claim 21 , wherein the error signature analysis module is further configured to:

determine whether the error signature value of a current bit is greater than the error threshold;

if the error signature value of the current bit is greater than the error threshold, determine whether the error signature values of the one or more pre-cursor bits are greater than the error threshold;

if either the error value of the current bit is not greater than the error threshold, or the error signature values of the one or more pre-cursor bits are greater than the error threshold:

determine whether the error value of the current bit is less than the minimum pulse response value of the receiver, wherein the minimum pulse response corresponds to the pulse response value of a last post-cursor bit of the current bit; and

increment a residual inter-symbol interference counter,

if the residual inter-symbol interference counter is greater than a predetermined threshold:

compute an average residual inter-symbol interference value; and

update the tap values based on the average residual inter-symbol interference value.

30. The receiver of claim 21 , wherein the error signature analysis module is configured to, at least one of: (i) adapt each tap value by a predetermined step value, and (ii) adapt each tap value by one of a course step value and a fine step value based on a gear-shifting value of the error signature analysis module.

31. The receiver of claim 21 , wherein the communication channel is a long-reach serializer/deserializer (SERDES) communication channel.

Assignments (11)
MERGER Recorded Mar 3, 2023
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; BROADCOM INTERNATIONAL PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 062952/0850 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER IN THE INCORRECT US PATENT NO. 8,876,094 PREVIOUSLY RECORDED ON REEL 047351 FRAME 0384. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 8, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 049248/0558 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF THE MERGER PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0910. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047351/0384 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0910 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 8, 2012
From: CHMELAR, ERIK V.
To: LSI CORPORATION
Reel/Frame 027672/0985 →
Continuity (1)
Related Publication 20130202065A1 · Aug 8, 2013