Semiconductor device and manufacturing method thereof

1. A semiconductor device, comprising:

a logic circuit;

an interlayer insulating film formed above the logic circuit, the interlayer insulating film having a through hole penetrating therethrough;

a contact plug embedded in the through hole, a top face of the contact plug being flush with a top face of the interlayer insulating film, the contact plug being electrically connected to the logic circuit;

an amorphous silicon layer formed on the interlayer insulating film to have a recess at a position corresponding to the contact plug, a top part of the amorphous silicon layer is silicided into a silicide layer while leaving a lower part thereof as a non-silicide layer; and

a TFT formed on the amorphous silicon layer,

wherein a bottom face of the silicide layer at the recess reaches the top face of the contact plug.

2. The device of claim 1 ,

wherein a thickness of the amorphous silicon layer at the recess is thinner than that at the other portion.

3. A semiconductor device, comprising:

a logic circuit;

an interlayer insulating film formed above the logic circuit, the interlayer insulating film having a through hole penetrating therethrough;

a contact plug embedded in the through hole, a top face of the contact plug being flush with a top face of the interlayer insulating film, the contact plug being electrically connected to the logic circuit;

a metal layer formed on the top face of the contact plug;

an amorphous silicon layer formed on the interlayer insulating film to cover the metal layer, a top part of the amorphous silicon layer is silicided into a silicide layer while leaving a lower part thereof as a non-silicide layer; and

a TFT formed on the amorphous silicon layer,

wherein a bottom face of the silicide layer reaches a top face of the metal layer.

4. The device of claim 3 ,

wherein the top face of the metal layer contacts the silicide layer, while a side face thereof contacts the non-silicide layer.

5. A semiconductor device, comprising:

a logic circuit;

an interlayer insulating film formed above the logic circuit;

an amorphous silicon layer comprising:

a non-silicide layer formed on the interlayer insulating film; and

a silicide layer formed on the non-silicide layer;

a TFT formed on the amorphous silicon layer; and

a contact plug formed to plug a through hole penetrating the interlayer insulating film, the contact plug being electrically connected to the logic circuit, an upper part of the contact plug being connected to the silicide layer;

wherein the contact plug plugs a part of the through hole to have a predetermined height,

wherein the amorphous silicon layer plugs a remaining part of the through hole above the contact plug, and

wherein, on the contact plug, the amorphous silicon is silicided into the silicide layer to reach the contact plug.

6. The device of claim 5 ,

wherein a height of the amorphous silicon layer on the contact plug is lower than that on the interlayer insulating film.

7. A semiconductor device manufacturing method, comprising:

forming a contact plug in a through hole that is formed in an interlayer insulating film provided on a logic circuit;

forming an amorphous silicon layer on the interlayer insulating film and on the contact plug;

selectively etching the amorphous silicon layer on the contact plug to a predetermined height; and

siliciding the amorphous silicon layer from a top-part thereof to a predetermined depth.