Gate stack of fin field effect transistor with slanted sidewalls
View Patent ↗The description relates to a gate stack of a fin field effect transistor (FinFET). An exemplary structure for a FinFET includes a substrate including a first surface and an insulation region covering a portion of the first surface, where a top of the insulation region defines a second surface. The FinFET further includes a fin disposed through an opening in the insulation region to a first height above the second surface, where a base of an upper portion of the fin is broader than a top of the upper portion, wherein the upper portion has first tapered sidewalls and a third surface. The FinFET further includes a gate dielectric covering the first tapered sidewalls and the third surface and a conductive gate strip traversing over the gate dielectric, where the conductive gate strip has second tapered sidewalls along a longitudinal direction of the fin.
1. A Fin field effect transistor (FinFET) comprising:
a substrate comprising a first surface;
an insulation region covering a portion of the first surface, wherein a top of the insulation region defines a second surface;
a fin disposed through an opening in the insulation region to a first height above the second surface, wherein a base of an upper portion of the fin is broader than a top of the upper portion, wherein the upper portion has first tapered sidewalls and a third surface;
a gate dielectric covering the first tapered sidewalls and the third surface; and
a conductive gate strip traversing over the gate dielectric, wherein the conductive gate strip has second tapered sidewalls along a longitudinal direction of the fin perpendicular to the first height, and the conductive gate strip is broader in the longitudinal direction of the fin at a base of the second tapered sidewalls than at a top of the second tapered sidewalls.
2. The FinFET of claim 1 , wherein the first height is in the range of about 20 nm to 50 nm.
3. The FinFET of claim 1 , wherein the fin comprises at least one of Si, Ge, a compound semiconductor or an alloy semiconductor.
4. The FinFET of claim 1 , wherein an angle of the second tapered sidewalls to the first surface is from about 85 degree to 88 degree.
5. The FinFET of claim 1 , wherein a ratio of a maximum width of the second tapered sidewalls to a minimum width of the second tapered sidewalls is from 1.05 to 1.25.
6. The FinFET of claim 1 , wherein the conductive gate strip comprises poly-silicon.
7. The FinFET of claim 1 , wherein the conductive gate strip comprises at least one metal selected from a group of W, Cu, Ti, Ag, Al, TiAl, TiAlN, TaC, TaCN, TaSiN, Mn, or Zr.
8. The FinFET of claim 1 , wherein the conductive gate strip comprises at least one metal selected from a group of TiN, WN, TaN, or Ru.
9. The FinFET of claim 1 , wherein the conductive gate strip further comprises a substantially vertical portion over the second tapered sidewalls.
10. The FinFET of claim 1 , wherein the gate dielectric comprises at least one of silicon oxide, silicon nitride, or silicon oxy-nitride.
11. The FinFET of claim 1 , wherein the gate dielectric comprises a high-k dielectric.
12. The FinFET of claim 1 , further comprises an interfacial layer between the third surface and the gate dielectric.
13. The FinFET of claim 12 , wherein the interfacial layer comprises silicon oxide.
14. The FinFET of claim 1 , wherein an angle of the first tapered sidewalls to the first surface is from about 84 degrees to 88 degrees.
15. The FinFET of claim 14 , wherein a difference between a maximum width of the first tapered sidewalls and a width of the third surface is in the range of about 1.5 nm to 5 nm.
16. The FinFET of claim 1 , wherein the fin further comprises a lower portion extending downward from the base of the upper portion to the first surface and having a second height, wherein the lower portion has third tapered sidewalls.
17. The FinFET of claim 16 , wherein an angle of the third tapered sidewalls to the first surface is from about 60 degrees to 85 degrees.
18. The FinFET of claim 16 , wherein a ratio of the first height to the second height is from about 0.2 to 0.5.
19. The FinFET of claim 16 , wherein the upper portion and the lower portion comprise the same material.
20. The FinFET of claim 16 , wherein the upper portion and the lower portion comprise different materials.