Data recovery using existing reconfigurable read channel hardware
A method for recovering data is disclosed. A sensed analog signal is converted into digital samples using an analog-to-digital converter (ADC). The digital samples are processed into processed digital samples using a first filter. The processed digital samples are decoded into decoded data. Whether the decoded data is acceptable is then determined. The processed digital samples are fed back to the first filter using a reprocessing circuit such that the processed digital samples are reprocessed into reprocessed digital samples in the event that the decoded data is unacceptable. A set of reprocessing coefficients is provided for the first filter to reprocess the processed digital samples.
1. A data recovery system, comprising:
an analog-to-digital converter (ADC) converting a sensed analog signal into digital samples;
a first filter processing the digital samples into processed digital samples;
a decoder decoding the processed digital samples into decoded data and determining whether the decoded data is acceptable;
a reprocessing circuit feeding the processed digital samples back to the first filter to be reprocessed into reprocessed digital samples in the event that the decoded data is unacceptable; and
a memory providing a set of reprocessing coefficients for the first filter to reprocess the processed digital samples.
2. The data recovery system of claim 1 , wherein the processed digital samples are stored in a storage, and wherein feeding the processed digital samples back to the first filter comprises retrieving the processed digital samples from the storage and feeding the retrieved samples back to the first filter to be reprocessed.
3. The data recovery system of claim 1 , wherein the reprocessed digital samples are decoded by the decoder into reprocessed decoded data.
4. The data recovery system of claim 1 , wherein the processing of the digital samples by the first filter is performed during a normal mode, and wherein the reprocessing of the processed digital samples by the first filter is performed during a reprocessing mode.
5. The data recovery system of claim 4 , wherein the data recovery system is configured to run in the normal mode or the reprocessing mode, but not concurrently, and wherein a same piece of hardware corresponding to the first filter is used in the normal mode and the reprocessing mode.
6. The data recovery system of claim 4 , wherein the sensed analog signal is received from a storage media during the normal mode but not during the reprocessing mode.
7. The data recovery system of claim 1 , further comprising a multiplexer configured to select the digital samples and forward the digital samples to the first filter as an input during a normal mode and further configured to select the processed digital samples that is feedback by the reprocessing circuit and forward the processed digital samples to the first filter as an input during a reprocessing mode.
8. The data recovery system of claim 1 , wherein the first filter comprises a finite impulse response (FIR) filter, and wherein processing the digital samples comprises equalizing the digital samples.
9. The data recovery system of claim 1 , further comprising a timing adjustment circuit adjusting sample phases of the ADC at least in part based on the digital samples during a normal mode, and wherein the reprocessing circuit is further configured to feed the processed digital samples back to the timing adjustment circuit as an input during a reprocessing mode and in the event that the decoded data is unacceptable, and wherein the timing adjustment circuit determines during the reprocessing mode phase adjustment information for adjusting the timing is phase of the reprocessed digital samples based at least in part on the processed digital samples.
10. The data recovery system of claim 9 , wherein the decoder comprises an error-correcting code (ECC) decoder, and wherein the timing adjustment circuit determines during the reprocessing mode phase adjustment information for adjusting the timing phase of the reprocessed digital samples based at least in part on bit decisions output by the ECC decoder.
11. The data recovery system of claim 9 , wherein the decoder comprises a soft output Viterbi algorithm (SOVA) module, and wherein the timing adjustment circuit determines during the reprocessing mode phase adjustment information for adjusting the timing phase of the reprocessed digital samples based at least in part on bit decisions output by the SOVA module.
12. The data recovery system of claim 9 , further comprising a second filter processing the digital samples during the normal mode, and wherein the reprocessing circuit is further configured to feed the processed digital samples back to the second filter as an input during the reprocessing mode and in the event that the decoded data is unacceptable, and wherein the phase adjustment information determined by the timing adjustment circuit is used to lookup a lookup table for a set of coefficients for the second filter, and wherein the output of the second filter is fed as an input to the first filter for adjusting the timing of the reprocessed digital samples during the reprocessing mode.
13. A method for recovering data, comprising:
converting a sensed analog signal into digital samples using an analog-to-digital converter (ADC);
processing the digital samples into processed digital samples using a first filter;
decoding the processed digital samples into decoded data and determining whether the decoded data is acceptable;
feeding the processed digital samples back to the first filter using a reprocessing circuit such that the processed digital samples are reprocessed into reprocessed digital samples in the event that the decoded data is unacceptable; and
providing a set of reprocessing coefficients for the first filter to reprocess the processed digital samples.
14. The method of claim 13 , further comprising storing the processing digital samples in a storage, and wherein feeding the processed digital samples back to the first filter comprises retrieving the processed digital samples from the storage and feeding the retrieved samples back to the first filter to be reprocessed.
15. The method of claim 13 , further comprising decoding the reprocessed digital samples into reprocessed decoded data using the decoder.
16. The method of claim 13 , wherein the processing of the digital samples using the first filter is performed during a normal mode, and wherein the reprocessing of the processed digital samples using the first filter is performed during a reprocessing mode.
17. The method of claim 16 , wherein the normal mode and the reprocessing mode are not run concurrently, and wherein a same piece of hardware corresponding to the first filter is used in the normal mode and the reprocessing mode.
18. The method of claim 16 , further comprising reading from a storage media to obtain the sensed analog signal during the normal mode but not during the reprocessing mode.
19. The method of claim 13 , further comprising configuring a multiplexer to select the digital samples and forward the digital samples to the first filter as an input during a normal mode, and further comprising configuring the multiplexer to select the processed digital samples that is feedback by the reprocessing circuit and forward the processed digital samples to the first filter as an input during a reprocessing mode.
20. The method of claim 13 , wherein the first filter comprises a finite impulse response (FIR) filter, and wherein processing the digital samples comprises equalizing the digital samples.