IP Library Granted Patent US 8,633,466
Granted Patent B2
US 8,633,466 · App. 13/371,823 · Granted Jan 21, 2014

Compound semiconductor device, method for producing the same, and power supply

Inventor: Naoya Okamoto (Kawasaki, JP)
Assignee: Fujitsu Limited
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Quick Facts
Patent No.
US 8,633,466
App. No.
13/371,823
Granted
Jan 21, 2014
Kind
B2
Abstract

A compound semiconductor device includes: a substrate; a first compound semiconductor layer formed over the substrate; a second compound semiconductor layer formed over the first compound semiconductor layer; and an upper electrode formed over the first compound semiconductor layer, wherein two-dimensional hole gas is generated in a region of the first compound semiconductor layer, the region being located at an interface between the first compound semiconductor layer and the second compound semiconductor layer, so as to have a hole concentration that decreases with increasing distance from the upper electrode.

Claims (37)

1. A compound semiconductor device comprising:

a substrate;

a first compound semiconductor layer formed over the substrate;

a second compound semiconductor layer formed over the first compound semiconductor layer; and

an upper electrode formed over the first compound semiconductor layer,

wherein two-dimensional hole gas is generated in a region of the first compound semiconductor layer, the region being located at an interface between the first compound semiconductor layer and the second compound semiconductor layer, so as to have a hole concentration that decreases with increasing distance along a direction parallel to the substrate from the upper electrode.

2. The compound semiconductor device according to claim 1 , wherein the second compound semiconductor layer has a stepped structure in which a thickness of the second compound semiconductor layer decreases stepwise with increasing distance from the upper electrode.

3. The compound semiconductor device according to claim 1 , wherein the second compound semiconductor layer is composed of a compound semiconductor containing aluminum or indium, and a content of aluminum or indium of the second compound semiconductor layer decreases with increasing distance from the upper electrode.

4. The compound semiconductor device according to claim 1 , wherein the second compound semiconductor layer includes a plurality of thick-film portions separated by a plurality of grooves, and a width of the plurality of thick-film portions decreases stepwise with increasing distance from the upper electrode.

5. The compound semiconductor device according to claim 1 ,

wherein the first compound semiconductor layer is composed of a gallium nitride-based semiconductor, and

the second compound semiconductor layer is composed of one semiconductor selected from a gallium nitride-based semiconductor containing aluminum, a gallium nitride-based semiconductor containing indium, and a gallium nitride-based semiconductor containing aluminum and indium.

6. The compound semiconductor device according to claim 1 , further comprising:

a lower electrode formed on a back surface of the substrate.

7. A method for producing a compound semiconductor device, comprising:

forming a first compound semiconductor layer over a substrate;

forming a second compound semiconductor layer over the first compound semiconductor layer; and

forming an upper electrode over the first compound semiconductor layer,

wherein two-dimensional hole gas is generated in a region of the first compound semiconductor layer, the region being located at an interface between the first compound semiconductor layer and the second compound semiconductor layer, so as to have a hole concentration that decreases with increasing distance along a direction parallel to the substrate from the upper electrode.

8. The method according to claim 7 , wherein the second compound semiconductor layer is formed so as to have a stepped structure in which a thickness of the second compound semiconductor layer decreases stepwise with increasing distance from the upper electrode.

9. The method according to claim 7 , wherein the second compound semiconductor layer is composed of a compound semiconductor containing aluminum or indium, and a content of aluminum or indium of the second compound semiconductor layer decreases with increasing distance from the upper electrode.

10. The method according to claim 9 , wherein the forming the second compound semiconductor layer includes

forming a mask having an opening for an area where the second compound semiconductor layer is to be formed, and

by molecular beam epitaxy, making aluminum or indium incident at a first angle tilted away from the upper electrode with reference to a line normal to the substrate, and making another material element incident at a second angle tilted toward the upper electrode with reference to the normal line, and

the second angle is larger than the first angle.

11. The method according to claim 7 , wherein a plurality of grooves are formed in the second compound semiconductor layer such that the second compound semiconductor layer includes a plurality of thick-film portions separated by the plurality of grooves, and a width of the plurality of thick-film portions decreases stepwise with increasing distance from the upper electrode.

12. The method according to claim 7 , wherein the first compound semiconductor layer is composed of a gallium nitride-based semiconductor, and

the second compound semiconductor layer is composed of one semiconductor selected from a gallium nitride-based semiconductor containing aluminum, a gallium nitride-based semiconductor containing indium, and a gallium nitride-based semiconductor containing aluminum and indium.

13. The method according to claim 7 , further comprising:

forming a lower electrode on a back surface of the substrate.

14. A power supply comprising

a Power Factor Correction circuit including a diode and a switching element, at least one of the diode and the switching element is a compound semiconductor device, the compound semiconductor device including

a substrate,

a first compound semiconductor layer formed over the substrate,

a second compound semiconductor layer formed aver the first compound semiconductor layer, and

an upper electrode formed over the first compound semiconductor layer, wherein

two-dimensional hole gas is generated in a region of the first compound semiconductor layer, the region being located at an interface between the first compound semiconductor layer and the second compound semiconductor layer, so as to have a hole concentration that decreases with increasing distance from the upper electrode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2012
From: OKAMOTO, NAOYA
To: FUJITSU LIMITED
Reel/Frame 027750/0860 →
Priority Claims (1)
JP 2011-040507 · Feb 25, 2011 · national
Continuity (1)
Related Publication 20120218796A1 · Aug 30, 2012