Silicon controlled rectifier based electrostatic discharge protection circuit with integrated JFETs, method of operation and design structure

1. An enhanced turn-on time silicon controlled rectifier (SCR) based electrostatic discharge (ESD) protection circuit comprising an integrated JFET is electrically connected with an NPN base, wherein

the JFET is electrically connected with a p-well resistor, and allows high resistance contact during an ESD event which lowers trigger current/voltage of the JFET, compared to a non-ESD event, and

the high resistance contact is formed when the JFET pinch-off gate voltage is in the 3 V to 5V range.

2. The enhanced SCR of claim 1 , wherein the JFET prevents SCR mis-triggering.

3. The enhanced SCR of claim 1 , wherein the JFET reduces turn-on time of the SCR.

4. The enhanced SCR of claim 1 , wherein the JFET is pinched off during the ESD event.

5. The enhanced SCR of claim 1 , wherein the JFET allows low resistance during the non-ESD event.

6. An enhanced turn-on time silicon controlled rectifier (SCR) based electrostatic discharge (ESD) protection circuit comprising an integrated JFET electrically connected with an NPN base and with a p-well resistor, wherein

the JFET allows low resistance during a non-ESD event, and

the low resistance includes about 3V or less on an I/O pad.

7. An enhanced turn-on time silicon controlled rectifier (SCR) based electrostatic discharge (ESD) protection circuit comprising an integrated JFET device electrically connected with an NPN base and also electrically connected with a p-well resistor, wherein the JFET device has an off resistance about three orders of magnitude higher than an on resistance.

8. An enhanced turn-on time silicon controlled rectifier (SCR) based electrostatic discharge (ESD) protection circuit comprising an integrated JFET device electrically connected with an NPN base and with a p-well resistor, wherein the JFET device has a pinch off voltage in a range of about 3V to 5V.

9. The enhanced SCR of claim 8 , wherein the pinch off of the JFET device increases SCR resistance and lowers trigger current, Itrig of a string of diodes of the SCR.

10. An operation of an enhanced turn-on time silicon controlled rectifier (SCR) based electrostatic discharge (ESD) protection circuit comprising an integrated JFET device electrically connected with an NPN base and with a p-well resistor, comprising lowering a trigger current of the JFET device by having a resistance of the JFET device increase.

11. The operation of claim 10 , further comprising increasing the resistance of the JFET when a gate voltage is high.

12. The operation of claim 10 , wherein when an I/O pad voltage is about 0 V to 3 V, the JFET device looks like a shunt or low resistance device.

13. The operation of claim 10 , wherein when an I/O pad voltage is about 0 to 3V, the JFET device looks like an on device, thereby providing low resistance to ground.

14. A hardware description language (HDL) design structure stored on a tangible machine-readable data storage medium comprising a non-volatile storage medium, the HDL design structure comprising elements that are processed in a computer-aided design system generates a machine-executable representation of an SCR, wherein the SCR comprises an integrated JFET electrically connected with an NPN base and with a p-well resistor, wherein the JFET device has an off resistance about three orders of magnitude higher than an on resistance.

15. The design structure of claim 14 , wherein the design structure comprises a netlist.

16. The design structure of claim 14 , wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.

17. The design structure of claim 14 , wherein the design structure resides in a programmable gate array.

18. The design structure of claim 14 , wherein the JFET device has a pinch off voltage in a range of about 3V to 5V.

19. The operation of claim 10 , wherein the JFET device allows high resistance contact during ESD event which lowers trigger current/voltage of the JFET device, compared to a non-ESD event, and the high resistance contact is formed when the JFET pinch-off gate voltage is in the 3 V to 5V range.

20. The operation of claim 10 , wherein the JFET device allows low resistance during a non-ESD event, and the low resistance includes about 3V or less on an I/O pad.

21. The operation of claim 10 , wherein the JFET device has an off resistance about three orders of magnitude higher than an on resistance.

22. The operation of claim 10 , wherein the JFET device has a pinch off voltage in a range of about 3V to 5V.