Fast lock clock-data recovery for phase steps
A clock-data recovery system and method promotes fast adjustment to large phase changes in the incoming data signal. The system can include phase alignment circuitry, clock generator circuitry, time-to-digital converter circuitry, and sampling circuitry. The phase alignment circuitry uses the incoming data signal and a feedback clock signal to generate an output clock signal. The clock generator circuitry uses the output clock signal to generate base phase clock signals of different phases or polarities. The time-to-digital converter circuitry uses the base phase clock signals and the incoming data signal to generate the feedback clock signal. The time-to-digital converter circuitry bases the feedback clock signal on the base phase clock signal that is aligned more closely in phase with the incoming data signal than the other base phase clock signals. The sampling circuitry re-times or recovers the data signal using one or more of the base phase clock signals.
1. A clock-data recovery system, comprising:
phase alignment circuitry generating an output clock signal in response to an incoming data signal and a feedback clock signal;
clock generator circuitry generating a plurality of base phase clock signals in response to the output clock signal, each base phase clock signal of the plurality of base phase clock signals differing in at least one of phase and polarity from all other base phase clock signals of the plurality of base phase clock signals and having a frequency the same as the frequency of all other base phase clock signals of the plurality of base phase clock signals;
time-to-digital converter circuitry generating the feedback clock signal in response to the incoming data signal and the plurality of base phase clock signals and in response to assertion of a re-lock signal indicating a large change in phase between the incoming data signal and the output clock signal, the time-to-digital converter circuitry basing the feedback clock signal on one of the plurality of base phase clock signals aligned more closely in phase with the incoming data signal than others of the plurality of base phase clock signals; and
sampling circuitry generating a recovered data signal in response to at least one of the plurality of base phase clock signals.
2. The clock-data recovery system of claim 1 , wherein the time-to-digital converter circuitry generates the feedback clock signal further in response to a data header encoded in the incoming data signal following assertion of the re-lock signal.
3. The clock-data recovery system of claim 1 , wherein the time-to-digital converter circuitry bases the feedback clock signal on one of the plurality of base phase clock signals by generating a plurality of output phase clock signals corresponding to the base phase clock signals but shiftable in phase from the plurality of base phase clock signals, and wherein the feedback clock signal is generated in response to one of the output phase clock signals.
4. The clock-data recovery system of claim 3 , wherein the time-to-digital converter circuitry comprises:
a thermometer code-to-binary code converter generating a phase select signal in response to at least a subset of the plurality of base phase clock signals; and
a shifter multiplexer generating the output phase clock signals in response to the base phase clock signals and the phase select signal, the phase select signal indicating one of the output phase clock signals to select as the feedback clock signal.
5. The clock-data recovery system of claim 3 , wherein:
the plurality of output phase clock signals consists of eight output phase clock signals; and
the plurality of base phase clock signals consists of eight base phase clock signals.
6. The clock-data recovery system of claim 3 , wherein:
the plurality of output phase clock signals comprises a sequence of clock signals increasing in phase by a uniform phase increment; and
the plurality of base phase clock signals comprises a sequence of clock signals increasing in phase by the uniform phase increment.
7. The clock-data recovery system of claim 3 , wherein the phase alignment circuitry comprises a phase detector, a loop filter and a voltage-controlled oscillator, the phase detector producing an output in response to the incoming data signal and the feedback clock signal, the loop filter producing an output in response to the output of the phase detector, and the voltage-controlled oscillator producing the output clock signal in response to the output of the loop filter.
8. The clock-data recovery system of claim 3 , wherein the sampling circuitry generates the recovered data signal in response to the plurality of output phase clock signals.
9. A clock-data recovery method, comprising:
generating an output clock signal in response to an incoming data signal and a feedback clock signal;
generating a plurality of base phase clock signals in response to the output clock signal, each base phase clock signal of the plurality of base phase clock signals differing in at least one of phase and polarity from all other base phase clock signals of the plurality of base phase clock signals and having a frequency the same as the frequency of all other base phase clock signals of the plurality of base phase clock signals;
generating the feedback clock signal in response to the incoming data signal and the plurality of base phase clock signals and in response to assertion of a re-lock signal indicating a large change in phase between the incoming data signal and the output clock signal by basing the feedback clock signal on one of the plurality of base phase clock signals aligned more closely in phase with the incoming data signal than others of the plurality of base phase clock signals; and
generating a recovered data signal in response to at least one of the plurality of base phase clock signals.
10. The clock-data recovery method of claim 9 , wherein generating the feedback clock signal comprises generating the feedback signal in response to a data header encoded in the incoming data signal following assertion of the re-lock signal.
11. The clock-data recovery method of claim 9 , wherein the feedback clock signal is based on one of the plurality of base phase clock signals by generating a plurality of output phase clock signals corresponding to the base phase clock signals but shiftable in phase from the plurality of base phase clock signals, and wherein the feedback clock signal is generated in response to one of the output phase clock signals.
12. The clock-data recovery method of claim 11 , wherein generating the feedback clock signal comprises:
generating a phase select signal in response to at least a subset of the plurality of base phase clock signals; and
generating the output phase clock signals in response to the base phase clock signals and the phase select signal, the phase select signal indicating one of the output phase clock signals to select as the feedback clock signal.
13. The clock-data recovery method of claim 11 , wherein:
the plurality of output phase clock signals consists of eight output phase clock signals; and
the plurality of base phase clock signals consists of eight base phase clock signals.
14. The clock-data recovery method of claim 11 , wherein:
the plurality of output phase clock signals comprises a sequence of clock signals increasing in phase by a uniform phase increment; and
the plurality of base phase clock signals comprises a sequence of clock signals increasing in phase by the uniform phase increment.
15. The clock-data recovery method of claim 11 , wherein generating the recovered data signal occurs in response to the plurality of output phase clock signals.
16. An integrated circuit device including a clock-data recovery system, comprising a monolithic substrate on which is formed:
means for generating an output clock signal in response to an incoming data signal and a feedback clock signal;
means for generating a plurality of base phase clock signals in response to the output clock signal, each base phase clock signal of the plurality of base phase clock signals differing in at least one of phase and polarity from all other base phase clock signals of the plurality of base phase clock signals and having a frequency the same as the frequency of all other base phase clock signals of the plurality of base phase clock signals;
means for generating the feedback clock signal in response to the incoming data signal and the plurality of base phase clock signals and in response to assertion of a re-lock signal indicating a large change in phase between the incoming data signal and the output clock signal, the means for generating the feedback clock signal basing the feedback clock signal on one of the plurality of base phase clock signals aligned more closely in phase with the incoming data signal than others of the plurality of base phase clock signals; and
means for generating a recovered data signal in response to at least one of the plurality of base phase clock signals.
17. The integrated circuit device of claim 16 , wherein the means for generating the feedback clock signal bases the feedback clock signal on one of the plurality of base phase clock signals by generating a plurality of output phase clock signals corresponding to the base phase clock signals but shiftable in phase from the plurality of base phase clock signals, and wherein the feedback clock signal is generated in response to one of the output phase clock signals.
18. The integrated circuit device of claim 17 , wherein the means for generating the feedback clock signal comprises:
means for generating a phase select signal in response to at least a subset of the plurality of base phase clock signals; and
means for generating the output phase clock signals in response to the base phase clock signals and the phase select signal, the phase select signal indicating one of the output phase clock signals to select as the feedback clock signal.