Non-systematic coded error correction
View Patent ↗Methods are described that facilitate the detection and correction of data in memory systems or devices by encoding the data bits of a memory row or block in a non-systematic ECC code. Reduced complexity error detection and correction hardware and/or routines detect and correct corrupted user data in a segment of memory, such as a sector, word line row, or erase block. User data is not stored in a plaintext format in the memory array. The ECC code is distributed throughout the stored data in the memory segment.
1. A method of operating a memory system comprising:
reading a non-systematic ECC encoded data segment of a plurality of segments from a selected memory device of one or more memory devices, wherein the one or more memory devices each contain a memory array with a plurality of memory cells arranged in one or more data segments; and
error checking and decoding the read non-systematic ECC encoded data segment as a single data block with a control circuit having a data buffer, a host transfer circuit coupled to the data buffer, and an ECC generator/checker circuit adapted to receive and decode the non-systematic ECC encoded data segment from the selected memory device and output to a data buffer; and
wherein the memory system is adapted to detect and correct errors in the non-systematic ECC encoded data segment as it is read from the selected memory device.
2. The method of claim 1 , further comprising:
transferring the decoded data segment from the memory system through a host interface.
3. The method of claim 1 , further comprising:
error correcting the non-systematic ECC encoded data segment if an error is detected.
4. The method of claim 3 , wherein error correcting the non-systematic ECC encoded data segment if an error is detected further comprises error correcting the non-systematic ECC encoded data segment in an internal data buffer.
5. The method of claim 3 , wherein error correcting the non-systematic ECC encoded data segment if an error is detected further comprises error correcting the non-systematic ECC encoded data segment by re-reading the non-systematic ECC encoded data segment and correcting the non-systematic ECC encoded data segment as it is read from the selected memory device.
6. The method of claim 3 , wherein error correcting the non-systematic ECC encoded data segment if an error is detected further comprises error correcting the non-systematic ECC encoded data segment by correcting the data segment at a host interface while it is being transferred from the memory system.
7. The method of claim 1 , wherein error checking and decoding the read non-systematic ECC encoded data segment further comprises error checking and decoding the read non-systematic ECC encoded data segment as the non-systematic ECC encoded data segment is transferred from the memory system through a host interface.
8. The method of claim 7 , wherein error checking and decoding the read non-systematic ECC encoded data segment as the non-systematic ECC encoded data segment is transferred from the memory system through a host interface further comprises aborting transfer of the decoded data segment at a host interface when an error is found.
9. The method of claim 1 , wherein the one or more memory devices are non-volatile memory devices.
10. The method of claim 9 , wherein the one or more non-volatile memory devices are one of a NOR architecture Flash memory device, a NAND architecture Flash memory device, a Polymer memory device, a Ferroelectric Random Access Memory (FeRAM) memory device, a Ovionics Unified Memory (OUM) memory device, Nitride Read Only Memory (NROM) memory device, and a Magnetoresistive Random Access Memory (MRAM) memory device.
11. The method of claim 1 , wherein the non-systematic ECC encoding is one of a Hamming code, a Reed-Solomon (R-S) code, a Bose-Chaudhuri-Hochquenghem (BCH) code, a circular redundancy code (CRC-32), a Golay code, a Reed-Muller code, a Goppa code, and a Denniston code.
12. The method of claim 1 , further comprising:
executing an error correction method if an error is detected.
13. The method of claim 12 , further comprising:
executing an error correction algorithm in a processor or a hardware correction circuit if an error is detected.
14. The method of claim 1 , further comprising:
presenting an interface to the memory system compatible with a mass storage device.
15. The method of claim 1 , further comprising:
encoding an input data segment with a non-systematic ECC code.
16. A method of operating a memory device comprising:
reading a non-systematic ECC encoded data segment from a memory array having a plurality of memory cells arranged in a plurality of segments; and
error checking and un-encoding the read non-systematic ECC encoded data segment as a single data block with a control circuit having a data buffer, a host transfer circuit coupled to the data buffer, and an ECC generator/checker circuit adapted to receive and un-encode the non-systematic ECC encoded data segment from the memory array and output to a data buffer; and
wherein the memory device is adapted to detect and correct errors in the non-systematic ECC encoded data segment as it is read from the memory array.
17. The method of claim 16 , wherein the memory array of the memory device is a one of NAND Flash memory array and a NOR Flash memory array.
18. The method of claim 16 , wherein the non-systematic ECC encoded data segment is encoded in one of a Hamming code, a Reed-Solomon (R-S) code, a Bose-Chaudhuri-Hochquenghem (BCH) code, a circular redundancy code (CRC-32), a Golay code, a Reed-Muller code, a Goppa code, and a Denniston code.
19. A method of operating a memory controller comprising:
receiving a non-systematic ECC encoded data segment from a selected memory device of one or more memory devices, wherein the one or more memory devices each contain a memory array with a plurality of memory cells arranged in one or more data segments; and
error checking and un-encoding the non-systematic ECC encoded data segment as a single data block with a control circuit having a data buffer, a host transfer circuit coupled to the data buffer, and an ECC generator/checker circuit adapted to receive and decode the non-systematic ECC encoded data segment from the selected memory device and output to a data buffer; and
wherein the memory controller is adapted to detect and correct errors in the non-systematic ECC encoded data segment as it is read from the selected memory device.
20. The method of claim 19 , wherein at least one of the one or more memory devices is a non-volatile memory device.
21. The method of claim 19 , wherein the non-systematic ECC encoded data segment is non-systematically encoded in one of a Hamming code, a Reed-Solomon (R-S) code, a Bose-Chaudhuri-Hochquenghem (BCH) code, a circular redundancy code (CRC-32), a Golay code, a Reed-Muller code, a Goppa code, and a Denniston code.
22. The method of claim 19 , further comprising:
encoding an input data segment with a non-systematic ECC code.
23. The method of claim 19 , further comprising:
transferring the decoded data segment from the memory controller through a host interface.
24. The method of claim 19 , further comprising:
error correcting the non-systematic ECC encoded data segment if an error is detected.
25. The method of claim 21 , wherein error correcting the non-systematic ECC encoded data segment if an error is detected further comprises error correcting the non-systematic ECC encoded data segment in an internal data buffer.
26. The method of claim 21 , wherein error correcting the non-systematic ECC encoded data segment if an error is detected further comprises error correcting the non-systematic ECC encoded data segment by re-receiving the non-systematic ECC encoded data segment and correcting the non-systematic ECC encoded data segment as it is received from the selected memory device.
27. The method of claim 19 , wherein error checking and decoding the read non-systematic ECC encoded data segment further comprises error checking and decoding the read non-systematic ECC encoded data segment as the non-systematic ECC encoded data segment is transferred from the memory controller through a host interface.
28. The method of claim 27 , wherein error checking and decoding the read non-systematic ECC encoded data segment as the non-systematic ECC encoded data segment is transferred from the memory system through a host interface further comprises aborting transfer of the decoded data segment at a host interface when an error is found.
29. The method of claim 19 , further comprising:
executing an error correction method if an error is detected.
30. The method of claim 29 , further comprising:
executing an error correction algorithm in a processor or a hardware correction circuit if an error is detected.
31. The method of claim 19 , further comprising:
presenting an interface to the memory controller compatible with a mass storage device.