Scan test circuitry with delay defect bypass functionality
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having scan cells. The scan test circuitry further comprises scan delay defect bypass circuitry comprising multiplexers arranged within the scan chain. At least a given one of the multiplexers is configured to allow a corresponding one of the scan cells to be selectively bypassed in a scan shift configuration of the scan cells responsive to a delay defect associated with that scan cell. A delay defect bypass controller may be used to generate a bypass control signal for controlling the multiplexer between at least a first state in which the corresponding scan cell is not bypassed and a second state in which the corresponding scan cell is bypassed.
1. An integrated circuit comprising:
scan test circuitry; and
additional circuitry subject to testing utilizing the scan test circuitry;
the scan test circuitry comprising at least one scan chain having a plurality of scan cells;
the scan test circuitry further comprising scan delay defect bypass circuitry comprising a plurality of multiplexers arranged within said at least one scan chain with at least a given one of the multiplexers being configured to allow a corresponding one of the scan cells to be selectively bypassed in a scan shift mode of operation responsive to a delay defect associated with that scan cell.
2. The integrated circuit of claim 1 wherein in the scan shift mode of operation the scan cells of the scan chain form a serial shift register operative to receive an applied test pattern.
3. The integrated circuit of claim 1 wherein select states of the respective multiplexers are controlled by a delay defect bypass controller.
4. The integrated circuit of claim 3 wherein the delay defect bypass controller is implemented at least in part within the scan delay defect bypass circuitry of the scan test circuitry.
5. The integrated circuit of claim 4 wherein the delay defect bypass controller comprises a test data register configured to store at least one bypass control bit for each of the plurality of multiplexers.
6. The integrated circuit of claim 1 wherein the plurality of multiplexers comprises a plurality of two-to-one multiplexers.
7. The integrated circuit of claim 1 wherein the given multiplexer comprises:
a first input coupled to a scan input of the corresponding one of the scan cells to be selectively bypassed;
a second input coupled to a scan output of the corresponding one of the scan cells to be selectively bypassed;
an output coupled to a scan input of a subsequent scan cell of the scan chain; and
a select line adapted for receiving a bypass control signal for controlling the multiplexer between at least a first state in which the corresponding scan cell is not bypassed and a second state in which the corresponding scan cell is bypassed.
8. The integrated circuit of claim 7 wherein the bypass control signal is generated by a delay defect bypass controller.
9. The integrated circuit of claim 1 wherein the scan cells of the scan chain comprise respective alternating resettable and settable flip-flops.
10. The integrated circuit of claim 9 wherein a first one of the scan cells of the scan chain comprises a resettable flip-flop, a second one of the scan cells comprises a settable flip-flop, and a third one of the scan cells comprises a resettable flip-flop, with that alternating pattern continuing for the remainder of the scan chain.
11. The integrated circuit of claim 9 wherein reset inputs of the resettable flip-flops and set inputs of the settable flip-flops are each coupled to a common control signal line such that upon assertion of that common control signal line a test pattern comprising a predetermined alternating sequence of logic 1 and logic 0 values is automatically loaded into the scan cells of the scan chain.
12. The integrated circuit of claim 1 wherein the multiplexers are inserted in locations in the scan chain that are determined by performing a timing analysis on timing paths between respective pairs of the scan cells.
13. The integrated circuit of claim 1 wherein the multiplexers are inserted in the scan chain so as to permit selective bypass of only those scan cells having respective associated timing paths with timing slacks below a specified threshold value.
14. A disk drive controller comprising the integrated circuit of claim 1 .
15. A method comprising:
configuring at least one scan chain to include a plurality of scan cells; and
bypassing at least a selected one of the scan cells of the scan chain in a scan shift mode of operation responsive to a delay defect associated with that scan cell.
16. The method of claim 15 wherein the step of bypassing at least a selected one of the scan cells comprises bypassing one or more of the scan cells in accordance with logic levels of respective bypass control bits stored for those scan cells in a test data register.
17. The method of claim 15 wherein the step of bypassing at least a selected one of the scan cells comprises applying a bypass control signal to a select line of a multiplexer arranged in a timing path associated with the selected scan cell to control the multiplexer between at least a first state in which the corresponding scan cell is not bypassed and a second state in which the corresponding scan cell is bypassed.
18. The method of claim 15 further comprising the steps of:
applying a test pattern to the scan cells of the scan chain in the scan shift mode of operation;
determining a location of a delay defect based on the test pattern; and
bypassing the scan cell associated with the location of the delay defect.
19. A computer program product comprising a non-transitory computer-readable storage medium having computer program code embodied therein for use in scan testing an integrated circuit, wherein the computer program code when executed in a testing system causes the testing system to perform the steps of the method of claim 15 .
20. A processing system comprising:
a processor; and
a memory coupled to the processor and configured to store information characterizing an integrated circuit design;
wherein the processing system is configured to provide scan test circuitry within the integrated circuit design, the scan test circuitry comprising at least one scan chain having a plurality of scan cells;
the scan test circuitry further comprising scan delay defect bypass circuitry comprising a plurality of multiplexers arranged within said at least one scan chain with at least a given one of the multiplexers being configured to allow a corresponding one of the scan cells to be selectively bypassed in a scan shift mode of operation responsive to a delay defect associated with that scan cell.