Semiconductor device and method of manufacturing semiconductor device
A semiconductor device has a substrate; a multi-layered interconnect formed on the substrate, and having a plurality of interconnect layers, each of which being configured by an interconnect and an insulating layer, stacked therein; a memory circuit formed in a memory circuit region on the substrate in a plan view, and having a peripheral circuit and at least one capacitor element embedded in the multi-layered interconnect; and a logic circuit formed in a logic circuit region on the substrate, wherein the capacitor element is configured by a lower electrode, a capacitor insulating film, an upper electrode, an embedded electrode and an upper interconnect; the top surface of the upper interconnect, and the top surface of the interconnect configuring the logic circuit formed in the same interconnect layer with the upper interconnect, are aligned to the same plane.
1. A semiconductor device comprising:
a substrate;
a multi-layered interconnect formed on said substrate, and having a plurality of interconnect layers, each of which being configured by an interconnect and an insulating layer, stacked therein;
a memory circuit formed in a memory circuit region on said substrate in a plan view, and having a peripheral circuit and at least one capacitor element embedded in said multi-layered interconnect; and
a logic circuit formed in a logic circuit region on said substrate, which is a region different from said memory circuit region in a plan view,
said capacitor element being configured by a lower electrode, a capacitor insulating film, an upper electrode, an embedded electrode and an upper interconnect,
said upper interconnect and said embedded electrode being configured by the same material in an integrated manner,
at least one layer of said interconnect configuring said logic circuit is provided between said upper interconnect and said lower electrode, and
the top surface of said upper interconnect, and the top surface of said interconnect configuring said logic circuit formed in the same interconnect layer with said upper interconnect, are aligned to the same plane,
wherein said insulating layer of said multi-layered interconnect, having said capacitor element embedded therein, is provided in common with said insulating layer configuring said logic circuit, formed in the same layer with said capacitor element, and
said insulating layer has a dielectric constant smaller than that of silicon oxide film.
2. The semiconductor device as claimed in claim 1 ,
further comprising a metal diffusion blocking film commonly formed over the top surface of said upper interconnect, and over the top surface of said interconnect configuring said logic circuit, formed in the same interconnect layer with said upper interconnect.
3. The semiconductor device as claimed in claim 1 , comprising a sidewall protection film formed between said insulating layer and said lower electrode.
4. The semiconductor device as claimed in claim 3 ,
wherein said sidewall protection film is a deposited layer or a modified layer.
5. The semiconductor device as claimed in claim 4 ,
wherein said deposited layer has a density larger than that of said adjacent insulating layer.
6. The semiconductor device as claimed in claim 4 ,
wherein said modified layer contains at least one element composing said adjacent insulating layer.
7. The semiconductor device as claimed in claim 1 ,
wherein said upper interconnect and said interconnect configuring said logic circuit are composed of different materials.
8. The semiconductor device as claimed in claim 7 ,
wherein said upper interconnect is composed of tungsten, and said interconnect configuring said logic circuit is composed of copper or a copper-containing alloy.
9. The semiconductor device as claimed in claim 1 ,
wherein a material, which composes said upper interconnect and said interconnect configuring said logic circuit, is copper or a copper-containing alloy.
10. The semiconductor device as claimed in claim 1 ,
wherein a material composing at least one insulating film, out of the insulating films formed between said interconnect configuring said logic circuit, and an active element formed on the surface of said substrate, has a dielectric constant smaller than that of silicon oxide film.
11. The semiconductor device as claimed in claim 1 ,
wherein said capacitor element has a cylindrical geometry, and
said upper electrode and said capacitor insulating film are formed right under said extension electrode of said upper interconnect.
12. The semiconductor device as claimed in claim 1 ,
wherein said upper interconnect has height in the thickness-wise direction smaller than height, in the thickness-wise direction, of said interconnect configuring said logic circuit, formed in the same interconnect layer with said upper interconnect.
13. The semiconductor device as claimed in claim 1 ,
wherein at least one layer of interconnects of said plurality of interconnect layers formed over said capacitor element comprises at least one layer of fixed-potential interconnect and a plurality of signal interconnects,
said fixed-potential interconnect being electrically connected to said upper interconnect configuring said capacitor element.
14. The semiconductor device as claimed in claim 1 ,
said upper interconnect has a vertical interconnect extended in the thickness-wise direction so as to penetrate said upper electrode and said capacitor insulating film, and
said vertical interconnect being electrically connected to a fixed-potential interconnect, below said upper interconnect.
15. A semiconductor device comprising:
a substrate;
a multi-layered interconnect formed on said substrate, and having a plurality of interconnect layers, each of which being configured by an interconnect and an insulating layer, stacked therein;
a memory circuit formed in a memory circuit region on said substrate in a plan view, and having a peripheral circuit and at least one capacitor element embedded in said multi-layered interconnect; and
a logic circuit formed in a logic circuit region on said substrate, which is a region different from said memory circuit region in a plan view,
said capacitor element being configured by a lower electrode, a capacitor insulating film, an upper electrode, an embedded electrode and an upper interconnect,
said upper interconnect and said embedded electrode being configured by the same material in an integrated manner,
at least one layer of said interconnect configuring said logic circuit being provided between said upper interconnect and said lower electrode, and
difference in the level of height. between the top surface of said upper interconnect, and the top surface of said interconnect configuring said logic circuit formed in the same interconnect layer with the upper interconnect, being 30 nm or smaller,
wherein said insulating layer of said multi-layered interconnect, having said capacitor element embedded therein, is provided in common with said insulating layer configuring said logic circuit, formed in the same layer with said capacitor element, and
said insulating layer has a dielectric constant smaller than that of silicon oxide film.