Memory cell, a method for forming a memory cell, and a method for operating a memory cell

1. A memory cell, comprising:

a first two-terminal memory element;

a second two-terminal memory element;

a controller circuit configured to program the first two-terminal memory element to one or more states and the second two-terminal memory element to one or more states, wherein a state of the first two-terminal memory element and a state of the second two-terminal memory element are interdependent; and

a measuring circuit configured to measure a difference signal between a first two-terminal memory element signal associated with the state of the first two-terminal memory element and a second two-terminal memory element signal associated with the state of the second two-terminal memory element.

2. The memory cell according to claim 1 ,

wherein the controller circuit is configured to program the first two-terminal memory element and the second two-terminal memory element to different states.

3. The memory cell according to claim 1 ,

wherein the controller circuit is configured to program interdependently the first two-terminal memory element to a first state and the two-terminal memory element to a second state, and to program interdependently the first two-terminal memory element to a second state and the two-terminal memory element to a first state.

4. The memory cell according to claim 1 ,

wherein the first two-terminal memory element signal and the second two-terminal memory element signal each comprises a current signal.

5. The memory cell according to claim 1 ,

wherein the first two-terminal memory element and the second two-terminal memory element are arranged such that the first two-terminal memory element and the second two-terminal memory element are programmed to different states in response to a voltage applied across the first two-terminal memory element and the second two-terminal memory element.

6. The memory cell according to claim 3 ,

wherein the first state comprises a first resistance value and the second state comprises a second resistance value, wherein the first resistance value is different from the second resistance value.

7. The memory cell according to claim 1 ,

wherein the memory cell comprises a single bit memory cell.

8. The memory cell according to claim 1 ,

wherein the memory cell is configured to be programmed to a first bit value wherein the first two-terminal memory element is programmed to a first state and the two-terminal memory is programmed to a second state, and

wherein the memory cell is configured to be programmed to a second bit value wherein the first two-terminal memory element is programmed to a second state and the two-terminal memory element is programmed to a first state.

9. The memory cell according to claim 1 ,

wherein the memory cell is configured to be programmed to a first bit value wherein a first voltage is applied across the first two-terminal memory element and the second two-terminal memory element, and

wherein the memory cell is configured to be programmed to a second bit value wherein a second voltage is applied across the first two-terminal memory element and the second two-terminal memory element.

10. The memory cell according to claim 9 ,

wherein the first voltage is equal and opposite to the second voltage.

11. The memory cell according to claim 1 ,

wherein one of the first two-terminal memory element and the second two-terminal memory element is reverse connected with respect to a voltage applied across the first two-terminal memory element and the second two-terminal memory element.

12. The memory cell according to claim 11 ,

wherein the first two-terminal memory element and the second two-terminal memory element are electrically coupled between at least one bit line and at least one access transistor.

13. The memory cell according to claim 12 ,

wherein the at least one access transistor comprises

a first access transistor electrically coupled to the first two-terminal memory element; and

a second access transistor electrically coupled to the second two-terminal memory element.

14. The memory cell according to claim 12 ,

wherein the at least one access transistor is configured to control a current through the first two-terminal memory element and the second two-terminal memory element, wherein the difference between the currents through the first two-terminal memory element and the second two-terminal memory element determines the bit value of the memory cell.

15. The memory cell according to claim 1 , further comprising

at least one access transistor comprising:

a first source/drain region;

a second source/drain region; and

a gate region;

wherein the first source/drain region is electrically coupled to the first two-terminal memory element and the second two-terminal memory element;

wherein the second source/drain region is electrically coupled to a source line of the memory cell; and

wherein the gate region is electrically coupled to a word line of the memory cell.

16. The memory cell according to claim 1 ,

wherein the first two-terminal memory element and the second two-terminal memory element each comprises a magnetoresistive random access two-terminal memory element.

17. The memory cell according to claim 1 ,

wherein the first two-terminal memory element and the second two-terminal memory element each comprises a magnetic tunnel junction stack; wherein

the magnetic tunnel junction stack comprises

a free magnetic layer;

and a fixed magnetic layer separated from the free magnetic layer by an isolation layer.

18. The memory cell according to claim 17 ,

wherein at least one bit line is electrically coupled to the free magnetic layer of the first two-terminal memory element and the fixed magnetic layer of the second two-terminal memory element; and

wherein at least one access transistor is electrically coupled to the fixed magnetic layer of the first two-terminal memory element and the free magnetic layer of the second two-terminal memory element.

19. The memory cell according to claim 1 ,

wherein the first two-terminal memory element and second two-terminal memory element each comprises a conductive bridging random access memory element.

20. The memory cell according to claim 1 ,

wherein the first two-terminal memory element and second two-terminal memory element each comprises a resistive random access memory element.

21. The memory cell according to claim 1 , further comprising

at least one access transistor comprising:

a first source/drain region;

a second source/drain region; and

a gate region;

wherein the gate region is electrically coupled to a word line of the memory cell;

wherein the word line comprises a word line body region and a word line extension region configured at an angle to the word line body region, wherein the word line extension region is arranged between the first two-terminal memory element and the second two-terminal memory element.

22. The memory cell according to claim 21 , wherein the word line extension region forms a further access transistor configured to isolate a source/drain region electrically coupled to the first two-terminal memory element from a source/drain region electrically coupled to the second two-terminal memory element.

23. A memory cell, comprising:

a first two-terminal memory element;

a second two-terminal memory element;

a controller circuit; and

a measuring circuit,

wherein the controller circuit and the measuring circuit are configured to operate in a first mode or a second mode;

wherein in the first mode, the controller circuit is configured to program the first two-terminal memory element to one or more states and the second two-terminal memory element to one or more states, wherein a state of the first two-terminal memory element and a state of the second two-terminal memory element are interdependent; and the measuring circuit is configured to measure a difference signal between a first two-terminal memory element signal associated with the state of the first two-terminal memory element and a second two-terminal memory element signal associated with the state of the second two-terminal memory element; and

wherein in the second mode the controller circuit is configured to program one of the first two-terminal memory element and the second two-terminal memory element to one or more states; and the measuring circuit is configured to measure a signal in one of the first two-terminal memory element and the second two-terminal memory element associated with the state of the one of the first two-terminal memory element and the second two-terminal memory element.

24. A method for forming a memory cell, the method comprising:

forming a first two-terminal memory element;

forming a second two-terminal memory element; and

forming a controller circuit for programming the first two-terminal memory element to one or more states and the second two-terminal memory element to one or more states, wherein a state of the first two-terminal memory element and a state of the second two-terminal memory element are interdependent; and

forming a measuring circuit for measuring a difference signal between a first two-terminal memory element signal associated with the state of the first two-terminal memory element and a second two-terminal memory element signal associated with the state of the second two-terminal memory element.

25. The method according to claim 24 , further comprising:

reverse connecting one of the first two-terminal memory element and the second two-terminal memory element with respect to a voltage applied across the first two-terminal memory element and the second two-terminal memory element.

26. A method for operating a memory cell, the method comprising:

programming a first two-terminal memory element to one or more states and a second two-terminal memory element to one or more states, wherein a state of the first two-terminal memory element and a state of the second two-terminal memory element are interdependent; and

measuring a difference signal between a first two-terminal memory element signal associated with the state of the first two-terminal memory element and a second two-terminal memory element signal associated with the state of the second two-terminal memory element.