Adjusting sampling phase in a baud-rate CDR using timing skew
In described embodiments, a transceiver includes a baud-rate clock and data recovery (CDR) module with an eye sampler, and an adaptation module for adaptively setting parameters of various circuit elements, such as timing, equalizer and gain elements. Data sampling clock phase of the CDR module is set for sampling at, for example, near the center of a data eye detected by the eye sampler, and the phase of data error sampling latch(es) is skewed by the CDR module with respect to the phase of the data sampling latch. Since the error signal driving the timing adaptation contains the information of the pulse response that the CDR module encounters, the phase of timing error sampling latch(es) of the CDR module is skewed based on maintaining a relative equivalence of input pulse response residual pre-cursor and residual post-cursor with respect to the timing error sampling clock phase.
1. Apparatus for baud-rate timing recovery in a receiver comprising:
an eye sampler configured to sample a data eye from a data stream subject to equalization, the eye sampler including at least one data error sampler, at least one timing error sampler, and at least one data sampler;
a skew clock and data recovery (CDR) circuit configured to:
i) generate a data clock to each data sampler and to each data error sampler at a baud rate of the data stream, wherein the skew CDR positions, in amplitude and phase, the data clock so as to position the data sampler about the center of the data eye, and
ii) generate a timing error clock from each timing error sampler, the timing error clock skewed by a phase offset from the data clock; and
the CDR circuit configured to adaptively adjust phases of the data clock and the timing error clock based on samples from each data sampler and each timing error sampler based on a predetermined criterion.
2. The apparatus of claim 1 , the CDR circuit further configured to:
adaptively set parameters of an equalizer applied to the data stream based upon outputs of each data error sampler and each data sampler, wherein each data error sampler samples in phase with the data clock.
3. The apparatus of claim 2 , wherein the equalizer is a decision feedback equalizer (DFE) of the receiver.
4. The apparatus of claim 2 , wherein the CDR circuit is coupled to a transmitter configured to provide the data stream,
wherein the transmitter, based on an indication of the CDR circuit, adaptively sets parameters of one or more devices of the transmitter in a signal path of the data stream, each device comprising at least one of a gain, a filter, and an equalizer.
5. The apparatus of claim 2 , wherein the CDR circuit is further configured to adaptively set parameters of at least one of a filter and a gain applied to the data stream.
6. The apparatus of claim 1 , wherein the CDR circuit is further configured to:
adaptively set parameters of an equalizer applied to the data stream based upon samples by each data error sampler and each data sampler.
7. The apparatus of claim 1 , wherein, at a convergence of the skew CDR circuit, a residual pre-cursor of the data stream is equivalent to a residual post-cursor of the data stream with respect with the sampling phase of each data error sampler.
8. The apparatus of claim 1 , wherein the skew CDR circuit implements a baud-rate CDR update of the data clock in accordance with a predetermined minimized-error criterion.
9. The apparatus of claim 8 , wherein the skew CDR circuit is a Mueller-Muller CDR.
10. The apparatus of claim 1 , wherein the apparatus is embodied in a Serial DeSerializer (SerDes) device.
11. A method of generating timing in a receiver comprising:
generating, by an eye sampler, a data eye from a data stream subject to equalization, the eye sampler including at least one data error sampler, at least one timing error sampler, and at least one data sampler;
generating, with a skew clock and data recovery (CDR) circuit,
i) a data clock to each data sampler and to each data error sampler at a baud rate of the data stream, wherein the skew CDR positions, in amplitude and phase, the data clock so as to position the data sampler about the center of the data eye, and
ii) a timing error clock from each timing error sampler, the timing error clock skewed by a phase offset from the data clock; and
adaptively adjusting phases of the data clock and the timing error clock based on samples from each data sampler and each timing error sampler based on a predetermined criterion.
12. The method of claim 11 , further comprising:
adaptively setting parameters of an equalizer applied to the data stream based upon outputs of each data error sampler and the data sampler, wherein each data error sampler samples in phase with the data clock.
13. The method of claim 12 , wherein the equalizer is a decision feedback equalizer (DFE) of the receiver.
14. The method of claim 12 , comprising:
providing, by a transmitter, the data stream, and
adaptively setting parameters of one or more devices of the transmitter in a signal path of the data stream based upon outputs of one or more of the at least one data error sampler, the at least one timing error sampler, and the at least one data sampler of the receiver.
15. The method of claim 12 , further comprising:
adaptively setting parameters of at least one of a filter and a gain applied to the data stream.
16. The method of claim 11 , further comprising:
adaptively setting parameters of an equalizer applied to the data stream based upon samples generated by one or more of the at least one data error sampler and the at least one data sampler.
17. The method of claim 11 , comprising converging operation of the skew CDR circuit, wherein, at a convergence, a residual pre-cursor of the data stream is equivalent to a residual post-cursor of the data stream with respect to the sampling phase of the data error sampler.
18. The method of claim 11 , comprising updating, by the skew CDR circuit, with a baud-rate CDR update of the data clock in accordance with a predetermined minimized-error criterion.
19. The method of claim 18 , wherein the skew CDR circuit updates in accordance with a Mueller-Muller algorithm.
20. A non-transitory machine-readable storage medium, having encoded thereon program code, wherein, when the program code is executed by a machine, the machine implements a method for generating timing in a receiver, comprising the steps of:
generating, by an eye sampler, a data eye from a data stream subject to equalization, the eye sampler including at least one data error sampler, at least one timing error sampler, and at least one data sampler;
generating, with a skew clock and data recovery (CDR) circuit,
i) a data clock to each data sampler and to each data error sampler at a baud rate of the data stream, wherein the skew CDR positions, in amplitude and phase, the data clock so as to position the data sampler about the center of the data eye, and
ii) a timing error clock from each timing error sampler, the timing error clock skewed by a phase offset from the data clock; and
adaptively adjusting phases of the data clock and the timing error clock based on samples from each data sampler and each timing error sampler based on a predetermined criterion.