Semiconductor devices with peripheral region insertion patterns
A semiconductor device includes a substrate including a memory cell region and a peripheral region and a field pattern including an insulating region disposed on a nitride liner in a trench in the substrate adjacent an active region. The field pattern and the active region extend in parallel through the cell and peripheral regions. The device also includes a transistor in the peripheral region including a source/drain region in the active region. The device further includes an insertion pattern including an elongate conductive region disposed in the substrate and extending along a boundary between the field pattern and the active region in the peripheral region. Fabrication methods are also described.
1. A semiconductor device comprising:
a substrate comprising a memory cell region and a peripheral region;
a field pattern comprising an insulating region disposed on a nitride liner in a trench in the substrate adjacent an active region, the field pattern and the active region extending in parallel through the cell and peripheral regions;
a transistor having a gate electrode on the active region in the peripheral region; and
an insertion pattern comprising an elongate conductive region disposed in the substrate and extending along a boundary between the field pattern and the active region in the peripheral region.
2. The semiconductor device of claim 1 , wherein the insertion pattern comprises:
a lower conductive portion; and
an upper insulating portion.
3. The semiconductor device of claim 1 , wherein the nitride liner does not extend between sidewalls of the insertion pattern and the field pattern.
4. The semiconductor device of claim 1 , further comprising
a contact electrically connected to the conductive region of the insertion pattern.
5. The semiconductor device of claim 4 , wherein the gate electrode crosses the active region and the field pattern.
6. The semiconductor device of claim 1 :
wherein the field pattern comprises first and second field patterns comprising respective insulating regions disposed on nitride liners in respective trenches in the substrate and extending in parallel through the cell and peripheral regions;
wherein the active region is disposed between the first and second field patterns; and
wherein the insertion pattern comprises first and second insertion patterns, each comprising an elongate conductive region disposed in the substrate and extending along respective first and second boundaries between the active region and second first and second field patterns.
7. The semiconductor device of claim 6 , wherein the transistor comprises a square-ring shaped gate electrode comprising opposing first line patterns extending in parallel with the active region and overlying the first and second insertion patterns and second opposing line patterns extending across the active region.
8. The semiconductor device of claim 1 , wherein the transistor is a PMOS transistor.
9. The semiconductor device of claim 8 , further comprising an NMOS transistor in the cell region and comprising a gate electrode crossing the active region.