Resistive memory and methods for forming the same
A device includes an active region formed of a semiconductor material, a gate dielectric at a surface of the active region, and a gate electrode over the gate dielectric. A first source/drain region and a second source/drain region are on opposite sides of the gate electrode. A Contact Etch Stop Layer (CESL) is over the first and the second source/drain regions. An Inter-Layer Dielectric (ILD) includes a top surface substantially level with a top surface of the gate electrode. A first contact plug is over and electrically connected to the first source/drain region. A second contact plug is over and aligned to the second source/drain region. The second contact plug and the second source/drain region are spaced apart from each other by a portion of the first CESL to form a capacitor.
1. A device comprising:
an active region comprising a semiconductor material;
a gate dielectric at a surface of the active region;
a gate electrode over the gate dielectric;
a first source/drain region and a second source/drain region on opposite sides of the gate electrode;
a first Contact Etch Stop Layer (CESL) over the first and the second source/drain regions;
a first Inter-Layer Dielectric (ILD) comprising a top surface substantially level with a top surface of the gate electrode;
a first contact plug over and electrically connected to the first source/drain region; and
a second contact plug over and aligned to the second source/drain region, wherein the second contact plug and the second source/drain region are spaced apart from each other by a portion of the first CESL to form a capacitor.
2. The device of claim 1 further comprising:
a second CESL over the top surface of the first ILD; and
a second ILD over the second CESL, wherein the first contact plug is in the first ILD and has a top surface substantially level with the top surface of the first ILD, and wherein and the second contact plug extends into the first ILD, the second CESL, and the second ILD.
3. The device of claim 2 , wherein the second CESL is substantially planar, and wherein top edges of the first CESL and top surfaces of the gate electrode and the first ILD are in contact with a bottom surface of the second CESL.
4. The device of claim 2 further comprising a third contact plug in the second CESL and the second ILD, wherein the first contact plug and the third contact plug are in contact with other, and have a visible interface.
5. The device of claim 1 further comprising a source/drain silicide region on a surface of the first source/drain region, wherein the first contact plug is in physical contact with the source/drain silicide region, and wherein no silicide region is formed between and aligned to the second contact plug and the second source/drain region.
6. The device of claim 1 , wherein the second contact plug comprises a bottom surface in physical contact with a top surface of the CESL.
7. The device of claim 1 , wherein the second contact plug and the second source/drain region are further spaced apart from each other by a lower portion of the first ILD.
8. A device comprising:
a semiconductor material;
a gate dielectric over the semiconductor material;
a gate electrode over the gate dielectric;
a first source/drain region and a second source/drain region on opposite sides of the gate electrode;
a source/drain silicide region over the first source/drain region;
a first Contact Etch Stop Layer (CESL) over the first and the second source/drain region;
a first Inter-Layer Dielectric (ILD) over the first CESL, wherein top edges of the first CESL, a top surface of the gate electrode, and a top surface of the first ILD are substantially level with each other;
a second CESL over the first CESL, the gate electrode, and the first ILD;
a second ILD over the second CESL;
a first contact plug over and connected to the source/drain silicide region; and
a second contact plug disposed in the first ILD, wherein the second contact plug is over and aligned to the second source/drain region, and wherein the second contact plug and the second source/drain region are spaced apart from each other by a portion of the first CESL.
9. The device of claim 8 , wherein the first contact plug has a top surface substantially level with the top surface of the first ILD, wherein the device further comprises a third contact plug over and contacting the first contact plug, and wherein the second and the third contact plugs are formed of a same material, and have top surfaces level with a top surface of the second ILD.
10. The device of claim 8 , wherein the first and the second contact plugs both comprise metals.
11. The device of claim 8 , wherein the first contact plug comprises a metal, and the second contact plug comprises polysilicon.
12. The device of claim 8 , wherein edges of the source/drain silicide region are aligned to respective edges of the first contact plug.
13. The device of claim 8 , wherein no silicide region is formed over and contacting the second source/drain region.
14. The device of claim 8 further comprising a gate contact plug penetrating through the second CESL to contact the gate electrode, wherein the gate contact plug and the second contact plug are formed of a same material.
15. A method comprising:
forming a gate dielectric at a surface of an active region comprising a semiconductor material;
forming a gate electrode over the gate dielectric;
forming a first source/drain region and a second source/drain region on opposite sides of the gate electrode;
forming a first Contact Etch Stop Layer (CESL) over the first and the second source/drain regions;
forming a first Inter-Layer Dielectric (ILD) over the first CESL, wherein top edges of the first CESL, a top surface of the gate electrode, and a top surface of the first ILD are substantially level with each other;
etching the first CESL and the first ILD to form a first opening, wherein the first source/drain region is exposed through the first opening;
forming a first contact plug in the first opening, wherein the first contact plug is electrically connected to the first source/drain region;
etching the first ILD to form a second opening over and aligned to the second source/drain region, wherein the etching of the first ILD to form the second opening stops before at least a lower portion of the first CESL is etched; and
forming a second contact plug in the second opening, wherein the second contact plug and the second source/drain region are spaced apart from each other by the lower portion of the first CESL.
16. The method of claim 15 , wherein during the step of etching the first CESL and the first ILD to form the first opening, no portion of the first CESL and the first ILD over and aligned to the second source/drain region is etched.
17. The method of claim 15 further comprising:
forming a second CESL over the first CESL, the gate electrode, and the first ILD;
forming a second ILD over the second CESL; and
forming a third contact plug in the second CESL and the second ILD, wherein the third contact plug is over and in contact with the first contact plug, and wherein the second contact plug extends into the second CESL and the second ILD.
18. The method of claim 15 further comprising, after the first opening is formed, forming a source/drain silicide region at a surface of the first source/drain region and in the first opening, wherein the source/drain silicide region is in contact with the first source/drain region and the first contact plug.
19. The method of claim 15 , wherein the step of etching the first ILD to form the second opening stops on the first CESL.
20. The method of claim 15 , wherein the step of etching the first ILD to form the second opening stops before the first CESL is exposed and after an upper portion of the first ILD is etched.