Control fin heights in FinFET structures

1. A device comprising:

a semiconductor substrate;

a Shallow Trench Isolation (STI) region adjacent to a surface of the semiconductor substrate;

a first and a second semiconductor strip comprising sidewalls and ends contacting edges of the STI region, wherein the first and the second semiconductor strips have lengthwise directions aligned to a straight line;

a first and a second semiconductor fin over and joining the first and the second semiconductor strips, respectively, wherein fin heights of the first and the second semiconductor fins are smaller than about 400 Å, and wherein the semiconductor fin is comprised in a Fin Field-Effect Transistor (FinFET); and

a gate stack overlapping the STI region, wherein the gate stack is between the first and the second semiconductor fins, with no additional gate stack and no additional semiconductor fins between the gate stack and the first and the second semiconductor fins, and wherein the gate stack has a lengthwise direction perpendicular to the straight line.

2. The device of claim 1 , wherein the first and the second semiconductor fins have a spacing smaller than about 500 Å.

3. The device of claim 1 , wherein the FinFET further comprises:

a gate dielectric layer;

a metal layer over the gate dielectric layer; and

a polysilicon layer over the metal layer, wherein the gate dielectric layer, the metal layer, and the polysilicon layer extend on a top surface and sidewalls of the first semiconductor fin.

4. The device of claim 1 , wherein the first and the second semiconductor strips and the first and the second semiconductor fins are formed of a same semiconductor material.

5. A device comprising:

a substrate;

an isolation region at a top surface of the substrate; and

a first semiconductor fin, wherein the first semiconductor fin has a fin height smaller than about 400 Å, wherein the fin height is measured from a top surface of the first semiconductor fin to a top surface of the isolation region, and wherein an end of the semiconductor fin is aligned to an edge of the isolation region;

a first gate dielectric layer and a gate electrode layer forming a Fin Field-Effect Transistor (FinFET) with the first semiconductor fin;

a second gate dielectric layer overlapping a portion of the isolation region, wherein a bottom surface of the second gate dielectric layer is in contact with a top surface of the isolation region; and

a polysilicon layer overlapping the second gate dielectric layer, wherein the polysilicon layer and the first semiconductor fin have a spacing greater than about 200 Å.

6. The device of claim 5 further comprising a second semiconductor fin spaced apart from the first semiconductor fin, with the isolation region between the first and the second semiconductor fins, wherein edges of the first and the second semiconductor fins are substantially aligned to opposite edges of the isolation region, and wherein the first semiconductor fin and the second semiconductor fin have a distance smaller than about 500 Å.

7. The device of claim 6 , wherein a ratio of the fin height to the distance is smaller than about 13.

8. The device of claim 5 further comprising a semiconductor strip underlying and connected to the first semiconductor fin, wherein the semiconductor strip comprises an edge contacting the edge of the isolation region, and wherein the semiconductor strip and the first semiconductor fin are formed of a same semiconductor material.

9. The device of claim 1 , wherein the gate stack is spaced apart from the first and the second fins by a space greater than about 200 Å.

10. The device of claim 1 , wherein the gate stack is a dummy pattern, and is electrically floating.

11. The device of claim 1 , wherein the polysilicon layer is spaced apart from the FinFET.

12. The device of claim 5 , wherein the polysilicon layer is a dummy pattern, and is electrically floating.