IP Library › Granted Patent US 8,661,175
Granted Patent B2
US 8,661,175 · App. 13/151,115 · Granted Feb 25, 2014

Multiprocessor synchronization using region locks

Inventors: Kapil Sundrani (Clutterbuckganj, IN); Lakshmi Kanth Reddy Kakanuru (Bangalore, IN)
Assignee: LSI Corporation
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Quick Facts
Patent No.
US 8,661,175
App. No.
13/151,115
Granted
Feb 25, 2014
Kind
B2
Abstract

Disclosed is a method of synchronizing a plurality of processors accesses to at least one shared resource. One of a plurality of processors requests an exclusive region lock for a shared resource using a logical block address (LBA) of a dummy target. The LBA is defined in a region map that associates LBAs to shared resources. The exclusive region lock request is inserted as a node in a region lock tree of the dummy target. Access to the shared resource is granted based on a determination whether there is an existing region lock in the region lock tree that is overlaps with the new exclusive region lock request.

Claims (37)

1. A method of synchronizing a plurality of processors' accesses to at least one shared resource, comprising:

requesting, by one of said plurality of processors, an exclusive region lock for a shared resource using a logical block address (LBA) of a dummy target, said LBA defined in a region map that contains at least one LBA, the at least one LBA in said region map associated with said shared resource;

inserting said exclusive region lock request as a node in a region lock tree of said dummy target; and,

granting one of said plurality of processors access to said shared resource based on a determination whether there is a first existing region lock in the region lock tree that is overlapping with said exclusive region lock request.

2. The method of claim 1 , wherein all of said plurality of processors request exclusive region locks for said shared resource using the same LBA of said dummy target.

3. The method of claim 1 , wherein said region map associates shared resources with corresponding lock ranges.

4. The method of claim 1 , further comprising:

requesting, by one of said plurality of processors, an exclusive region lock for a second shared resource using a second LBA of said dummy target, said second LBA defined in said region map that contains a second at least one LBA, the second at least one LBA in said region map associated with said second shared resource.

5. The method of claim 4 , further comprising:

inserting said second exclusive region lock request as a second node in said region lock tree of said dummy target.

6. The method of claim 5 , further comprising:

granting one of said plurality of processors access to said shared resource based on a determination whether there is a second existing region lock on the region lock tree that is overlapping with said second exclusive region lock request.

7. The method of claim 5 , further comprising:

granting one of said plurality of processors access to said shared resource based on a determination whether there is a first existing region lock on the region lock tree that is overlapping with said exclusive region lock request and whether there is a second existing region lock on the region lock tree that is overlapping with said second exclusive region lock request.

8. The method of claim 1 , wherein said shared resource comprises nonvolatile memory.

9. The method of claim 1 , wherein said shared resource comprises resources used by input/output (I/O) operations.

10. A computer system, comprising:

a plurality of processors configured to access at least one shared resource by requesting an exclusive region lock for a shared resource using a logical block address (LBA) of a dummy target;

a region map containing said LBA and configured to contain a plurality of LBAs, said region map configured to associate said LBA with said shared resource;

a region lock tree of said dummy target configured to receive said exclusive region lock request as a node in said region lock tree of said dummy target; and,

said plurality of processors configured to receive access to said shared resource based on a determination whether there is a first existing region lock in the region lock tree that is overlapping with said exclusive region lock request.

11. The computer system of claim 10 , wherein all of said plurality of processors request exclusive region locks for said shared resource using the same LBA of said dummy target.

12. The computer system of claim 10 , wherein said region map associates shared resources with corresponding LBA ranges.

13. A computer readable medium having instructions stored thereon for synchronizing a plurality of processors accesses to at least one shared resource that, when executed by a computer, at least instruct the computer to:

request, by one of said plurality of processors, an exclusive region lock for a shared resource using a logical block address (LBA) of a dummy target, said LBA defined in a region map that contains at least one LBA, the at least one LBA in said region map associated with said shared resource;

insert said exclusive region lock request as a node in a region lock tree of said dummy target; and,

grant one of said plurality of processors access to said shared resource based on a determination whether there is a first existing region lock on the region lock tree that is overlapping with said exclusive region lock request.

14. The computer readable medium of claim 13 , wherein all of said plurality of processors request exclusive region locks for said shared resource using the same LBA of said dummy target.

15. The computer readable medium of claim 13 , wherein said region map associates shared resources with corresponding LBA ranges.

16. The computer readable medium of claim 13 , wherein the computer is further instructed to:

request, by one of said plurality of processors, an exclusive region lock for a second shared resource using a second LBA of said dummy target, said second LBA defined in said region map that contains a second at least one LBA, the second at least one LBA in said region map associated with said second shared resource.

17. The computer readable medium of claim 16 , wherein the computer is further instructed to:

insert said second exclusive region lock request as a second node in said region lock tree of said dummy target.

18. The computer readable medium of claim 17 , wherein the computer is further instructed to:

grant one of said plurality of processors access to said shared resource based on a determination whether there is a second existing region lock on the region lock tree that is overlapping with said second exclusive region lock request.

19. The computer readable medium of claim 17 , wherein the computer is further instructed to:

grant one of said plurality of processors access to said shared resource based on a determination whether there is a first existing region lock on the region lock tree that is overlapping with said exclusive region lock request and whether there is a second existing region lock on the region lock tree that is overlapping with said second exclusive region lock request.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER IN THE INCORRECT US PATENT NO. 8,876,094 PREVIOUSLY RECORDED ON REEL 047351 FRAME 0384. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 8, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 049248/0558 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF THE MERGER PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0910. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047351/0384 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0910 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 2, 2011
From: SUNDRANI, KAPIL; KAKANURU, LAKSHMI KANTH REDDY
To: LSI CORPORATION
Reel/Frame 026387/0026 →
Continuity (1)
Related Publication 20120311300A1 · Dec 6, 2012