Nitride semiconductor device
According to one embodiment, a nitride semiconductor device includes a first, a second and a third semiconductor layer, a first and a second main electrode and a control electrode. The first layer made of a nitride semiconductor of a first conductivity type is provided on a substrate. The second layer made of a nitride semiconductor of a second conductivity type is provided on the first layer. The third layer made of a nitride semiconductor is provided on the second layer. The first electrode is electrically connected with the second layer. The second electrode is provided at a distance from the first electrode and electrically connected with the second layer. The control electrode is provided within a first trench via an insulating film. The first trench is disposed between the first and the second main electrodes, penetrates the third and the second layers, and reaches the first layer.
1. A nitride semiconductor device comprising:
a first semiconductor layer made of a nitride semiconductor of a first conductivity type, provided on a substrate;
a second semiconductor layer made of a nitride semiconductor of a second conductivity type, provided on the first semiconductor layer and having a sheet carrier concentration being same as a sheet carrier concentration of the first semiconductor layer;
a third semiconductor layer made of a nitride semiconductor with a forbidden band width wider than a forbidden band width of the second semiconductor layer, provided on the second semiconductor layer;
a first main electrode electrically connected with the second semiconductor layer;
a second main electrode provided at a distance from the first main electrode and electrically connected with the second semiconductor layer; and
a control electrode provided within a first trench via an insulating film, the first trench being disposed between the first main electrode and the second main electrode, penetrating the third semiconductor layer and the second semiconductor layer, and extending into the first semiconductor layer.
2. The device according to claim 1 , wherein the third semiconductor layer includes a plurality of semiconductor layers having mutually different compositions, and
of the plurality of semiconductor layers, the semiconductor layer in contact with the second semiconductor layer has a forbidden band width wider than the forbidden band width of the second semiconductor layer.
3. The device according to claim 2 , wherein the third semiconductor layer includes an AlGaN layer, and
the AlGaN layer is in contact with the second semiconductor layer including GaN.
4. The device according to claim 2 , wherein the third semiconductor layer includes an AlN layer, and
the AlN layer is in contact with the second semiconductor layer including GaN.
5. The device according to claim 1 , wherein the second semiconductor layer includes:
a fourth semiconductor layer doped with impurities of the second conductivity type, and
a fifth semiconductor layer that is in contact with the third semiconductor layer and that has a concentration of impurities of the second conductivity type lower than that of the fourth semiconductor layer.
6. The device according to claim 5 , wherein the compositions of the fourth semiconductor layer and the fifth semiconductor layer are different.
7. The device according to claim 6 , wherein the fourth semiconductor layer includes AlGaN, and the fifth semiconductor layer includes GaN.
8. The device according to claim 1 , wherein the first semiconductor layer includes an AlGaN layer and a GaN layer.
9. The device according to claim 1 , wherein the first main electrode extends within a second trench penetrating the third semiconductor layer and the second semiconductor layer to reach the first semiconductor layer, and contacts the first semiconductor layer on an inside surface of the second trench.
10. The device according to claim 9 , wherein
the first main electrode includes a first ohmic electrode and a second ohmic electrode, and
the first ohmic electrode is in contact with the first semiconductor layer, and the second ohmic electrode is in contact with the third semiconductor layer.
11. The device according to claim 10 , wherein
the first ohmic electrode includes Ni and Ag, and
the second ohmic electrode includes Ti and Al.
12. The device according to claim 1 , further comprising a semiconductor region of the first conductivity type, provided directly below the first main electrode, and penetrating the third semiconductor layer and the second semiconductor layer to reach the first semiconductor layer.
13. The device according to claim 12 , wherein a carrier concentration of the semiconductor region is higher than a carrier concentration of the first semiconductor layer.
14. The device according to claim 12 , wherein
the first main electrode includes a first ohmic electrode and a second ohmic electrode, and
the first ohmic electrode is in contact with the first semiconductor region, and the second ohmic electrode is in contact with the third semiconductor layer.
15. The device according to claim 14 , wherein
the first ohmic electrode includes Ni and Ag, and
the second ohmic electrode includes Ti and Al.
16. The device according to claim 1 , further comprising a semiconductor region of the second conductivity type, provided directly below the second main electrode, and penetrating the third semiconductor layer and the second semiconductor layer to reach the first semiconductor layer.
17. The device according to claim 1 , wherein the insulating film provided within the first trench includes a silicon nitride film.
18. The device according to claim 1 , wherein the substrate is one of a sapphire substrate, a SIC substrate, and a GaN substrate.
19. The device according to claim 1 , further comprising a sixth semiconductor layer provided on the substrate and having a higher resistance than the first semiconductor layer and the second semiconductor layer,
the first semiconductor layer being provided between the second semiconductor layer and the sixth semiconductor layer.
20. The device according to claim 19 , wherein the sixth semiconductor layer is provided on the substrate via a buffer layer including a plurality of nitride semiconductor layers.