Transistor including insertion layer and channel layer with different work functions and method of manufacturing the same
A transistor according to example embodiments may include a channel layer, a source and a drain respectively contacting ends of the channel layer, a gate electrode separated from the channel layer, a gate insulating layer interposed between the channel layer and the gate electrode, and/or an insertion layer that is formed between the channel layer and the gate insulating layer. The insertion layer may have a work function different from that of the channel layer.
1. A transistor comprising:
a channel layer;
a source and a drain respectively contacting opposing ends of the channel layer;
a gate electrode isolated from the channel layer;
a gate insulating layer between the channel layer and the gate electrode; and
an insertion layer between the channel layer and the gate insulating layer, the insertion layer having a work function different from that of the channel layer, the insertion layer being formed of a different base material from the channel layer, the insertion layer being a semiconductor layer, the insertion layer being formed of a single layer, and the insertion layer directly contacting the channel layer and the gate insulating layer,
wherein the channel layer is an n-type semiconductor layer and the insertion layer is a p-type or an n-type semiconductor layer.
2. The transistor of claim 1 , wherein the channel layer includes an oxide.
3. The transistor of claim 2 , wherein the oxide is zinc oxide, copper oxide, or nickel oxide.
4. The transistor of claim 1 , wherein the channel layer is a zinc oxide layer doped with at least one of a group 13 element and a group 14 element.
5. The transistor of claim 1 , wherein the insertion layer has a work function greater than that of the channel layer.
6. The transistor of claim 5 , wherein the insertion layer has an energy band gap greater than that of the channel layer.
7. A transistor comprising:
a channel layer;
a source and a drain respectively contacting opposing ends of the channel layer;
a gate electrode isolated from the channel layer;
a gate insulating layer between the channel layer and the gate electrode; and
an insertion layer between the channel layer and the gate insulating layer, the insertion layer having a work function different from that of the channel layer, the insertion layer being formed of a different base material from the channel layer, the insertion layer being a semiconductor layer, the insertion layer being formed of a single layer, and the insertion layer directly contacting the channel layer and the gate insulating layer,
wherein the channel layer is a p-type semiconductor layer and the insertion layer is an n-type or a p-type semiconductor layer.
8. The transistor of claim 7 , wherein the channel layer is one of a copper oxide layer, a nickel oxide layer, and a zinc oxide layer, wherein the nickel oxide layer is optionally doped with a group 4 transition metal and the zinc oxide layer is doped with at least one of a group 1 element, a group 2 element, a group 15 element, and a transition metal.
9. The transistor of claim 7 , wherein the insertion layer has a work function smaller than that of the channel layer.
10. The transistor of claim 9 , wherein the insertion layer has an energy band gap smaller than that of the channel layer.
11. The transistor of claim 1 , wherein the gate electrode is above the channel layer.
12. The transistor of claim 1 , wherein the gate electrode is below the channel layer.
13. A method of manufacturing a transistor, comprising:
forming a channel layer and a gate electrode on a substrate, the channel layer isolated from the gate electrode;
forming a source and a drain on the substrate, the source and the drain respectively contacting opposing ends of the channel layer;
forming a gate insulating layer between the channel layer and the gate electrode; and
forming an insertion layer between the channel layer and the gate insulating layer, the insertion layer having a work function different from that of the channel layer, the insertion layer being formed of a different base material from the channel layer, the insertion layer being a semiconductor layer, the insertion layer being formed of a single layer, and the insertion layer directly contacting the channel layer and the gate insulating layer,
wherein the channel layer is an n-type or a p-type semiconductor layer and the insertion layer is a p-type or an n-type semiconductor layer.
14. The method of claim 13 , wherein the insertion layer is formed to have a work function greater than that of the channel layer.
15. The method of claim 13 , wherein the insertion layer is formed to have a work function smaller than that of the channel layer.
16. The method of claim 13 , wherein the gate electrode is formed above the channel layer.
17. The method of claim 13 , wherein the gate electrode is formed below the channel layer.
18. The transistor of claim 1 , wherein the work function of the insertion layer differs from a work function of the channel layer by about 0.1-4 eV.
19. The method of claim 13 , wherein the work function of the insertion layer differs from a work function of the channel layer by about 0.1-4 eV.
20. A transistor comprising:
a channel layer;
a source and a drain respectively contacting opposing ends of the channel layer;
a gate electrode isolated from the channel layer;
a gate insulating layer between the channel layer and the gate electrode; and
an insertion layer between the channel layer and the gate insulating layer, the insertion layer having a work function different from that of the channel layer, the insertion layer being formed of a different base material from the channel layer, and the insertion layer being a semiconductor layer,
wherein when the channel layer is an n-type semiconductor layer, the insertion layer has a work function greater than that of the channel layer and has an energy band gap greater than that of the channel layer, and when the channel layer is a p-type semiconductor layer, the insertion layer has a work function smaller than that of the channel layer and has an energy band gap smaller than that of the channel layer,
wherein the channel layer is an n-type or a p-type semiconductor layer and the insertion layer is a p-type or an n-type semiconductor layer.