Semiconductor device die with integrated MOSFET and low forward voltage diode-connected enhancement mode JFET and method

1. A semiconductor device die with integrated metal oxide semiconductor field effect transistor (MOSFET) and diode-connected enhancement mode JFET, the semiconductor device die comprising:

a lower common semiconductor substrate region (CSSR) of type-1 conductivity;

a MOSFET device region, located at the top of the CSSR, having:

the CSSR as its MOSFET drain region;

at least a MOSFET body region of type-2 conductivity, a MOSFET gate region and a MOSFET source region of type-1 conductivity located at the top of the MOSFET drain region; and

a diode-connected enhancement mode JFET (DCE-JFET) device region, located at the top of the CSSR, having:

the CSSR as its DCE-JFET drain region;

at least two DCE-JFET gate regions of type-2 conductivity located at the top of the DCE-JFET drain region and laterally separated from each other along the major CSSR plane with a DCE-JFET gate spacing;

at least a DCE-JFET source region of type-1 conductivity located at the top of the CSSR and between the DCE-JFET gate regions, wherein the DCE-JFET source region is shorted to the DCE-JFET gate regions; and

whereby the CSSR serially connects the MOSFET device drain region to the DCE-JFET device drain region.

2. The MOSFET-JFET semiconductor device die of claim 1 , wherein said semiconductor device die further comprises:

two conduction nodes Terminal-S and Terminal-D;

a source electrode connected to the MOSFET source region as the Terminal-S; and

a DCE-JFET electrode in contact with said DCE-JFET gate regions and DCE-JFET source regions, as the Terminal-D.

3. The MOSFET-JFET semiconductor device die of claim 1 wherein said MOSFET-JFET semiconductor device die is connected to a battery and to a battery charging source in a battery charging circuit.

4. The MOSFET-JFET semiconductor device die of claim 1 wherein conductivity level of the DCE-JFET gate regions, conductivity level of a DCE-JFET channel region between the DCE-JFET gate regions and under the DCE-JFET source region, and DCE-JFET gate spacing are all configured at their respectively pre-determined levels whereby making the DCE-JFET device exhibit a low forward voltage Vf and a low reverse leakage current as a diode-connected enhancement mode JFET.

5. The MOSFET-JFET semiconductor device die of claim 4 wherein said Vf is substantially lower than that of a PN junction diode while said reverse leakage current is comparable to that of a PN junction diode.

6. The MOSFET-JFET semiconductor device die of claim 1 wherein:

the dopant material, concentration and depth of the MOSFET body regions are selected to be the same as those of the DCE-JFET gate regions; and

the dopant material, concentration and depth of the MOSFET source regions are selected to be the same as those of the DCE-JFET source regions

whereby simplifying its manufacturing process.

7. The MOSFET-JFET semiconductor device die of claim 2 wherein material and thickness of the MOSFET source electrode is selected to be the same as those of the DCE-JFET electrode whereby simplifying its manufacturing process.

8. The MOSFET-JFET semiconductor device die of claim 1 wherein said MOSFET gate regions are configured as trench gates extending downwards into the MOSFET body regions and the CSSR.

9. The MOSFET-JFET semiconductor device die of claim 1 wherein said MOSFET gate regions are configured as planar gates located over the MOSFET body regions and bridging the MOSFET source regions to the CSSR.

10. The MOSFET-JFET semiconductor device die of claim 1 where said CSSR comprises an upper layer of lower type-1 conductivity atop a lower substrate layer of higher type-1 conductivity.

11. The MOSFET-JFET semiconductor device die of claim 1 wherein said type-1 conductivity is P-type and said type-2 conductivity is N-type whereby making the MOSFET-JFET semiconductor device die a P-channel device.

12. The MOSFET-JFET semiconductor device die of claim 1 wherein said type-1 conductivity is N-type and said type-2 conductivity is P-type whereby making the MOSFET-JFET semiconductor device die an N-channel device.

13. The MOSFET-JFET semiconductor device die of claim 1 wherein the semiconductor device die is a discrete power device.

14. A method of making a semiconductor device die with integrated MOSFET and diode-connected enhancement mode JFET (DCE-JFET) wherein:

the integrated MOSFET-JFET semiconductor device die has a lower common semiconductor substrate region (CSSR) of type-1 conductivity;

the MOSFET is located at the top of the CSSR and having:

the CSSR as its MOSFET drain region;

at least a MOSFET body region of type-2 conductivity, a MOSFET gate region and a MOSFET source region of type-1 conductivity located at the top of the drain region; and

the DCE-JFET is located at the top of the CSSR and having:

the CSSR as its DCE-JFET drain region;

at least two DCE-JFET gate regions of type-2 conductivity stacked atop the drain region and laterally separated from each other along the major CSSR plane with a DCE-JFET gate spacing; and

at least a DCE-JFET source region of type-1 conductivity stacked atop the CSSR between the DCE-JFET gate regions; wherein the DCE-JFET source region is shorted to the DCE-JFET gate regions,

the method comprises:

a) providing the CSSR, partitioning its major plane into a MOSFET zone and a DCE-JFET zone then fabricating a MOSFET gate region in the MOSFET zone;

b) creating the MOSFET body region in the MOSFET zone and the DCE-JFET gate regions in the DCE-JFET zone; and

c) creating the MOSFET source region in the MOSFET zone and the DCE-JFET source region in the DCE-JFET zone; and

d) shorting the DCE-JFET source region to the DCE-JFET gate regions.

15. The method of claim 14 , wherein said semiconductor device die further comprises two conduction nodes Terminal-S, Terminal-D,

wherein the MOSFET further comprises:

a top source electrode connected to the MOSFET source region as the Terminal-S,

wherein the DCE-JFET further comprises:

a top DCE-JFET electrode, located atop and in contact with said DCE-JFET gate regions and

the DCE-JFET source region, as the Terminal-D,

wherein the method further comprises:

e) forming and patterning a top metallization layer comprising:

the top source electrode of the MOSFET; and

the top DCE-JFET electrode.

16. The method of claim 14 further comprises configuring all of:

conductivity level of the DCE-JFET gate regions, conductivity level of a DCE-JFET channel region between the DCE-JFET gate regions and under the DCE-JFET source region, and DCE-JFET gate spacing

at their respectively pre-determined levels whereby making the DCE-JFET device simultaneously exhibit a low forward voltage Vf and a low reverse leakage current.

17. The method of claim 14 wherein creating the MOSFET body region and the DCE-JFET gate regions comprises:

making a first simultaneous implantation, with a first implantation mask, of first MOSFET implantation region in the MOSFET zone and first DCE-JFET implantation regions in the DCE-JFET zone; and

simultaneously diffusing and activating the first MOSFET implantation region and the first DCE-JFET implantation regions respectively into the MOSFET body regions and the DCE-JFET gate regions.

18. The method of claim 14 wherein creating the MOSFET source regions and the DCE-JFET source regions comprises:

making a second simultaneous implantation, with a second implantation mask, of second MOSFET implantation region in the MOSFET zone and second DCE-JFET implantation region in the DCE-JFET zone; and

simultaneously diffusing and activating the second MOSFET implantation region and the second DCE-JFET implantation region respectively into the MOSFET source region and the DCE-JFET source region.

19. The method of claim 15 wherein forming and patterning a top metallization layer comprises:

depositing a top metal layer atop the MOSFET zone and the DCE-JFET zone; and

patterning the formed top metal layer, through a top metal mask, such that:

a portion of patterned top metal layer in the MOSFET zone corresponds to the desired top source electrode; and

a portion of patterned top metal layer in the DCE-JFET zone corresponds to the desired top DCE-JFET electrode.