CMOS image sensor
A CIS and a method of manufacturing the same, the CIS including a substrate having a first surface and second surface opposite thereto, the substrate including an APS array region including a photoelectric transformation element and a peripheral circuit region; an insulating interlayer on the first surface of the substrate and including metal wirings electrically connected to the photoelectric transformation element; a light blocking layer on the peripheral circuit region of the second surface of the substrate, exposing the APS array region, and including a plurality of metal wiring patterns spaced apart from one another to form at least one drainage path along a boundary region between the APS array region and the peripheral circuit region; a color filter layer on the second surface of the substrate covering the APS array region and the light blocking layer; and a microlens on the color filter layer on the APS array region.
1. A complementary metal-oxide semiconductor (CMOS) image sensor (CIS), comprising:
a substrate having a first surface and a second surface opposite to the first surface, the substrate including:
an active pixel sensor (APS) array region, the APS array region including a photoelectric transformation element, and
a peripheral circuit region;
an insulating interlayer on the first surface of the substrate, the insulating interlayer including metal wirings electrically connected to the photoelectric transformation element;
a light blocking layer on the peripheral circuit region of the second surface of the substrate, the light blocking layer exposing the APS array region and including a plurality of metal wiring patterns spaced apart from one another to form at least one drainage path along a boundary region between the APS array region and the peripheral circuit region;
a color filter layer on the second surface of the substrate, the color filter layer covering the APS array region and the light blocking layer; and
a microlens on the color filter layer on the APS array region.
2. The CIS as claimed in claim 1 , wherein the drainage path of the light blocking layer is at a corner portion of the light blocking layer.
3. The CIS as claimed in claim 1 , wherein the drainage path of the light blocking layer is at a middle portion of the light blocking layer.
4. The CIS as claimed in claim 1 , wherein the metal wiring patterns form a plurality of drainage paths, the drainage paths being at a corner portion and a middle portion of the light blocking layer.
5. The CIS as claimed in claim 1 , wherein the light blocking layer includes aluminum.
6. The CIS as claimed in claim 1 , wherein the color filter layer has a uniform height along the boundary region between the APS array region and the peripheral circuit region.
7. The CIS as claimed in claim 1 , wherein the color filter layer has a uniform, flat surface across the APS array region, the peripheral circuit region, and the boundary region therebetween.
8. The CIS as claimed in claim 1 , wherein the metal wiring patterns surround the APS array region.
9. The CIS as claimed in claim 1 , wherein the color filter layer covers the light blocking layer in the peripheral circuit region.