Wiring substrate, method for manufacturing wiring substrate, and semiconductor package including wiring substrate
A wiring substrate includes a ceramic substrate including plural ceramic layers, an inner wiring, and an electrode electrically connected to the inner wiring, the electrode exposed on a first surface of the ceramic substrate, and a silicon substrate body having a front surface and a back surface situated on an opposite side of the front surface and including a wiring pattern formed on the front surface and a via filling material having one end electrically connected to the wiring pattern and another end exposed at the back surface. The back surface is bonded to the first surface of the ceramic substrate via a polymer layer. The via filling material penetrates through the polymer layer and is directly bonded to the electrode.
1. A wiring substrate comprising:
a ceramic substrate including a plurality of ceramic layers, an inner wiring, and an electrode electrically connected to the inner wiring, the electrode exposed on a first surface of the ceramic substrate;
a silicon substrate having a first surface and a second surface situated on an opposite side of the first surface and including a wiring pattern formed on the first surface and a via filling material having one end electrically connected to the wiring pattern and another end exposed at the second surface; and
an insulating layer formed on the silicon substrate;
wherein the silicon substrate includes a first via hole penetrating the silicon substrate from the first surface to the second surface,
wherein the first via hole includes a via hole part having an inner side surface on which the insulating layer is formed,
wherein the second surface of the silicon substrate is bonded to the first surface of the ceramic substrate via a polymer layer,
wherein the polymer layer includes a second via hole continuing to the first via hole,
wherein the first via hole has a diameter substantially equal to a diameter of the second via hole by having the insulating layer formed on the inner side surface of the via hole part,
wherein the via filling material penetrates through the polymer layer and is directly and integrally bonded to the electrode of the ceramic layer,
wherein the via filling material fills an inside of the first via hole and an inside of the second via hole.
2. The wiring substrate as claimed in claim 1 , wherein each of the plural ceramic layers contains alumina cordierite.
3. The wiring substrate as claimed in claim 2 , wherein each of the plural ceramic layers contains different amounts of alumina cordierite.
4. The wiring substrate as claimed in claim 3 , wherein one of the plural ceramic layers situated far from the silicon substrate has a higher coefficient of thermal expansion (CTE) than the CTE of another one of the plural ceramic layers situated near the silicon substrate.
5. The wiring substrate as claimed in claim 1 ,
wherein the insulating layer is formed on the first surface of the silicon substrate,
wherein the via filling material contacts the insulating layer and the polymer layer in a thickness direction of the silicon substrate and the polymer layer.
6. The wiring substrate as claimed in claim 1 , wherein the via hole part is formed of a part that has a diameter that is larger than a diameter of a surface of the electrode exposed on the first surface of the ceramic substrate, wherein the diameter of the second via hole is substantially equal to the diameter of the surface of the electrode exposed on the first surface of the ceramic substrate.