IP Library Granted Patent US 8,686,750
Granted Patent B2
US 8,686,750 · App. 13/101,387 · Granted Apr 1, 2014

Method for evaluating semiconductor device

Inventor: Koichiro Kamata (Isehara, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,686,750
App. No.
13/101,387
Granted
Apr 1, 2014
Kind
B2
Abstract

To provide a simple method for evaluating reliability of a transistor, a simple test which correlates with a bias-temperature stress test (BT test) is performed instead of the BT test. Specifically, a gate current value is measured in the state where a voltage lower than the threshold voltage of an n-channel transistor whose channel region includes an oxide semiconductor is applied between a gate and a source of the transistor and a potential applied to a drain is higher than a potential applied to the gate. The evaluation of the gate current value can be simply performed compared to the case where the BT test is performed; for example, it takes short time to measure the gate current value. That is, reliability of a semiconductor device including the transistor can be easily evaluated.

Claims (10)

1. A method for evaluating a semiconductor device, comprising the steps of:

measuring a gate current value in a state where a voltage lower than a threshold voltage of an n-channel transistor whose channel region comprises an oxide semiconductor is applied between a gate and a source of the transistor, and a potential applied to a drain is higher than a potential applied to the gate; and

evaluating reliability of the semiconductor device comprising the transistor, using the gate current value.

2. The method for evaluating a semiconductor device, according to claim 1 , wherein the voltage between the gate and the source of the transistor is negative.

3. The method for evaluating a semiconductor device, according to claim 1 , wherein the potential applied to the drain is zero.

4. A method for evaluating a semiconductor device, comprising the steps of:

measuring a variation in a gate current value with time in a state where a voltage lower than a threshold voltage of an n-channel transistor whose channel region comprises an oxide semiconductor is applied between a gate and a source of the transistor, and a potential applied to a drain is higher than a potential applied to the gate; and

evaluating reliability of the semiconductor device, comprising the transistor, using the variation in the gate current value with time.

5. The method for evaluating a semiconductor device, according to claim 4 , wherein the voltage between the gate and the source of the transistor is negative.

6. The method for evaluating a semiconductor device, according to claim 4 , wherein the potential applied to the drain is zero.

Assignments (3)
CONFIRMATORY LICENSE Recorded Jun 26, 2013
From: UNIVERSITY OF CENTRAL FLORIDA
To: NATIONAL INSTITUTES OF HEALTH (NIH), U.S. DEPT. OF HEALTH AND HUMAN SERVICES (DHHS), U.S. GOVERNMENT
Reel/Frame 030695/0310 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2011
From: DANIELL, HENRY
To: UNIVERSITY OF CENTRAL FLORIDA RESEARCH FOUNDATION, INC.
Reel/Frame 026680/0413 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 5, 2011
From: KAMATA, KOICHIRO
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 026230/0741 →
Priority Claims (1)
JP 2010-111158 · May 13, 2010 · national
Continuity (1)
Related Publication 20110279144A1 · Nov 17, 2011