Verification algorithm for metal-oxide resistive memory
Memory devices and methods for operating such devices are described which can effectively program the metal-oxide memory elements in an array, while also avoiding applying unnecessarily high voltage pulses. Programming operations described herein include applying a lower voltage pulse across a metal-oxide memory element to establish a desired resistance state, and only applying a higher voltage pulse when the lower voltage pulse is insufficient to program the memory element. In doing so, issues associated with applying unnecessarily high voltages across the memory element can be avoided.
1. A memory device comprising:
a metal-oxide memory element programmable to a plurality of resistance states; and
a controller including logic to apply bias arrangements to the metal-oxide memory element, the bias arrangements including:
a first bias arrangement to establish a first resistance state in the plurality of resistance states, the first bias arrangement comprising a first voltage pulse; and
a second bias arrangement to establish the first resistance state if the memory element is not in the first resistance state after applying the first bias arrangement, the second bias arrangement comprising a second voltage pulse having a pulse height across the metal-oxide memory element which is greater than that of the first voltage pulse, wherein the first resistance state corresponds to a resistance value higher than that of a second resistance state in the plurality of resistance states, and the bias arrangements further include:
a third bias arrangement to change the resistance state from the first resistance state to the second resistance state, the third bias arrangement comprising a third voltage pulse having a voltage polarity across the metal-oxide memory element the same as that of the first and second voltage pulses.
2. The memory device of claim 1 , wherein the logic applies the third bias arrangement during a programming operation which does not include a program-verify step.
3. The memory device of claim 1 , wherein the metal-oxide memory element comprises tungsten-oxide.
4. The memory device of claim 1 , wherein the bias arrangements further include:
a fourth bias arrangement to change the resistance state from the second resistance state to a third resistance state.
5. A memory device comprising:
a metal-oxide memory element programmable to a plurality of resistance states; and
a controller including logic to apply bias arrangements to the metal-oxide memory element, the bias arrangements including:
a first bias arrangement to establish a first resistance state in the plurality of resistance states, the first bias arrangement comprising a first voltage pulse; and
a second bias arrangement to establish the first resistance state if the memory element is not in the first resistance state after applying the first bias arrangement, the second bias arrangement comprising a second voltage pulse having a pulse height across the metal-oxide memory element which is greater than that of the first voltage pulse, wherein the first resistance state corresponds to a resistance value lower than that of a second resistance state in the plurality of resistance states, and the bias arrangements further include:
a third bias arrangement to change the resistance state from the first resistance state to the second resistance state, the third bias arrangement comprising a third voltage pulse having a voltage polarity across the metal-oxide memory element which is opposite that of the first and second voltage pulses.
6. The memory device of claim 5 , wherein the logic applies the third bias arrangement during a programming operation which does not include a program-verify step.
7. The memory device of claim 5 , wherein the controller further includes logic to iteratively apply subsequent bias arrangements to establish the first resistance state and read the resistance state of the memory element, the subsequent bias arrangements applied until the memory element is in the first resistance state or a predetermined number of retries are made, wherein the subsequent bias arrangements respectively comprise a corresponding voltage pulse having a pulse height across the metal-oxide memory element greater than that of the first voltage pulse.
8. The memory device of claim 5 , wherein the metal-oxide memory element comprises tungsten-oxide.
9. The memory device of claim 5 , wherein the bias arrangements further includes:
a fourth bias arrangement to change the resistance state from the second resistance state to a third resistance state.
10. A method for operating a metal-oxide memory element programmable to a plurality of resistance states, the method comprising:
applying a first bias arrangement to the metal-oxide memory element to establish a first resistance state in the plurality of resistance states, the first bias arrangement comprising a first voltage pulse;
determining whether the metal-oxide memory element is in the first resistance state after applying the first bias arrangement; and
if the memory element is not in the first resistance state, then applying a second bias arrangement to the metal-oxide memory element to establish the first resistance state, the second bias arrangement comprising a second voltage pulse having a pulse height across the metal-oxide memory element greater than that of the first voltage pulse, wherein the first resistance state corresponds to a resistance value higher than that of a second resistance state in the plurality of resistance states, and further comprising:
applying a third bias arrangement to the metal-oxide memory element to change the resistance state from the first resistance state to the second resistance state, the third bias arrangement comprising a third voltage pulse having a voltage polarity across the metal-oxide memory element which is the same as that of the first and second voltage pulses.
11. The method of claim 10 , further comprising performing a programming operation to change the resistance state of the memory element after applying the third bias arrangement, wherein no verify operation is performed between applying the third bias arrangement and performing the programming operation.
12. The method of claim 10 , wherein if the memory element is not in the first resistance state after applying the second bias arrangement, iteratively applying subsequent bias arrangements to the memory element until the memory element is in the first resistance state or a predetermined number of retries are made, wherein the subsequent bias arrangements respectively comprise a corresponding voltage pulse having a pulse height greater than that of the first voltage pulse.
13. The method of claim 10 , wherein the metal-oxide memory element comprises tungsten-oxide.
14. The method of claim 10 , further including
applying a fourth bias arrangement to change the resistance state from the second resistance state to a third resistance state.
15. A method for operating a metal-oxide memory element programmable to a plurality of resistance states, the method comprising:
applying a first bias arrangement to the metal-oxide memory element to establish a first resistance state in the plurality of resistance states, the first bias arrangement comprising a first voltage pulse;
determining whether the metal-oxide memory element is in the first resistance state after applying the first bias arrangement; and
if the memory element is not in the first resistance state, then applying a second bias arrangement to the metal-oxide memory element to establish the first resistance state, the second bias arrangement comprising a second voltage pulse having a pulse height across the metal-oxide memory element greater than that of the first voltage pulse, wherein the first resistance state corresponds to a resistance value lower than that of a second resistance state in the plurality of resistance states, and further comprising:
applying a third bias arrangement to the metal-oxide memory element to change the resistance state from the first resistance state to the second resistance state, the third bias arrangement comprising a third voltage pulse having a voltage polarity across the metal-oxide memory element opposite that of the first and second voltage pulses.
16. The method of claim 15 , further comprising performing a programming operation to change the resistance state of the memory element after applying the third bias arrangement, wherein no verify operation is performed between applying the third bias arrangement and performing the programming operation.
17. The method of claim 15 , wherein if the memory element is not in the first resistance state after applying the second bias arrangement, iteratively applying subsequent bias arrangements to the memory element until the memory element is in the first resistance state or a predetermined number of retries are made, wherein the subsequent bias arrangements respectively comprise a corresponding voltage pulse having a pulse height greater than that of the first voltage pulse.
18. The method of claim 15 , wherein the metal-oxide memory element comprises tungsten-oxide.
19. The method of claim 15 , further comprising:
applying a fourth bias arrangement to change the resistance state from the second resistance state to a third resistance state.
20. A memory device comprising:
a memory cell including a metal-oxide memory element programmable to a plurality of resistance states; and
a controller including logic operable to program a selected memory cell to a data value to:
determine if the data value corresponds to a first resistance state or a second resistance state of the metal-oxide memory element;
perform a first program operation with verify if the data value corresponds to the first resistance state; and
perform a second program operation without verify if the data value corresponds to the second resistance state, wherein:
the first resistance state corresponds to a resistance value lower than that of the second resistance state;
the logic to perform a first program operation applies a first voltage pulse across the metal-oxide memory element; and
the logic to perform a second program operation applies a second voltage pulse across the metal-oxide memory element, the second voltage pulse having a voltage polarity opposite that of the first voltage pulse.
21. The memory device of claim 20 , wherein the memory cell is a multibit cell, and the controller includes logic to perform program operations for at least one additional resistance state.
22. A memory device comprising:
a memory cell including a metal-oxide memory element programmable to a plurality of resistance states; and
a controller including logic operable to program a selected memory cell to a data value to:
determine if the data value corresponds to a first resistance state or a second resistance state of the metal-oxide memory element;
perform a first program operation with verify if the data value corresponds to the first resistance state; and
perform a second program operation without verify if the data value corresponds to the second resistance state, wherein:
the first resistance state corresponds to a resistance value greater than that of the second resistance state;
the logic to perform a first program operation applies a first voltage pulse across the metal-oxide memory element; and
the logic to perform a second program operation applies a second voltage pulse across the metal-oxide memory element, the second voltage pulse having a voltage polarity the same as that of the first voltage pulse.
23. The memory device of claim 22 , wherein the memory cell is a multibit cell, and the controller includes logic to perform program operations for at least one additional resistance state.