IP Library › Granted Patent US 8,713,397
Granted Patent B2
US 8,713,397 · App. 13/105,527 · Granted Apr 29, 2014

Apparatus and method for layered decoding in a communication system using low-density parity-check codes

Inventors: Hyun-Koo Yang (Seoul, KR); Hong-Sil Jeong (Seoul, KR); Se-Ho Myung (Suwon-si, KR); Jae-Yoel Kim (Suwon-si, KR)
Assignee: Samsung Electronics Co., Ltd
H03M13/114H03M13/116H03M13/1137H03M13/1177H03M13/00
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Quick Facts
Patent No.
US 8,713,397
App. No.
13/105,527
Granted
Apr 29, 2014
Kind
B2
Abstract

A channel decoding apparatus and method in a communication system using Low-Density Parity-Check (LDPC) codes are provided in which an encoded signal is received from a transmitter and decoded using a parity-check matrix. At least one of input orders and output orders of the parity-check matrix are determined so that same values are not overlapped in a column direction between the at least one of the input orders and the output orders.

Claims (18)

1. A channel decoding method comprising the steps of:

extracting a parity-check matrix;

grouping rows of the parity-check matrix into one or more groups;

grouping rows of each group into one or more sub-groups, if the each group has two or more non-zero elements in a column direction; and

determining input and/or output orders for each row of the one or more sub-groups,

wherein each row of the one or more sub-groups is processed in parallel.

2. The channel decoding method of claim 1 , wherein grouping rows comprises:

grouping rows of the parity-check matrix to avoid overlapping input and/or output values in the column direction between rows of each group.

3. The channel decoding method of claim 1 , wherein determining comprises:

determining at least one of the input orders and the output orders of the grouped rows to avoid overlapping input and/or output values in the column direction between layers of each group.

4. The channel decoding method of claim 1 , wherein, when a Quasi-Cyclic Low-Density Parity-Check (QC-LDDC) code is layer-decoded, input and/or output values are not overlapped in the column direction between adjacent layers in the parity check matrix, wherein the QC-LDPC has one block being a sum of two or more permutation matrices.

5. A channel decoding apparatus comprising:

an extractor for extracting a parity-check matrix; and

a controller for grouping rows of the parity-check matrix into one or more groups, grouping rows of each group into one or more sub-groups, if the each group has two or more non-zero elements in a column direction, and determining input and/or output orders for each row of the one or more sub-groups,

wherein each row of the one or more sub-groups is processed in parallel.

6. The channel decoding apparatus of claim 5 , wherein the controller groups the rows of the parity-check matrix so that input and/or output values are not overlapped in the column direction between rows of each group.

7. The channel decoding apparatus of claim 5 , wherein at least one of the input orders and the output orders of the grouped rows are determined so that input and/or output values are not overlapped in the column direction between layers of each group.

8. The channel decoding apparatus of claim 5 , wherein when a Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) code is layered-decoded, input and/or output values are not overlapped in the column direction between adjacent layers in the parity check matrix, wherein the QC-LDPC has one block being a sum of two or more permutation matrices.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 9, 2011
From: YANG, HYUN-KOO; JEONG, HONG-SIL; MYUNG, SE-HO; KIM, JAE-YOEL
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 026414/0763 →
Priority Claims (1)
KR 10-2010-0044165 · May 11, 2010 · national
Continuity (1)
Related Publication 20110283158A1 · Nov 17, 2011