Zero voltage switching interleaved boost AC/DC converter
View Patent ↗Circuits and methods relating to the provision of a reactive current to ensure zero voltage switching in a boost power factor correction converter. A simple passive circuit using a series connected inductor and capacitor are coupled between two phases of an interleaved boost PFC converter. The passive circuit takes advantage of the 180° phase-shift between the two phases to provide reactive current for zero voltage switching. A control system for adjusting and controlling the reactive current to ensure ZVS for different loads and line voltages is also provided.
1. A circuit for use in a power factor correction (PFC) converter circuit having a full bridge diode rectifier subcircuit, the circuit comprising:
first inductor coupled between a positive input node and a first intermediate node;
a second inductor coupled between said positive input node and a second intermediate node;
a first power transistor having a drain lead coupled to said first intermediate node and having a source lead coupled to a negative power node;
a second power transistor having a source lead coupled to said first intermediate node and a drain lead coupled to a positive output node;
a third power transistor having a drain lead coupled to said second intermediate node and having a source lead coupled to said negative power node;
a fourth power transistor having a source lead coupled to said second intermediate node and a drain lead coupled to said positive output node; and
an auxiliary inductor and an auxiliary capacitor coupled in series to one another between said first intermediate node and said second intermediate node;
wherein
said full bridge rectifier subcircuit is coupled between said positive input node and said negative power node;
a load to said circuit is coupled between said positive output node and said negative power node.
2. A circuit according to claim 1 wherein each power transistor is equipped with a snubber diode.
3. A circuit according to claim 1 wherein each power transistor is equipped with a capacitor coupled between each transistor's drain and source leads.
4. A circuit according to claim 1 wherein each power transistor is a metal-oxide-semiconductor field effect transistor (MOSFET).
5. A circuit according to claim 1 wherein said full bridge diode rectifier subcircuit receives an AC input current.
6. A circuit according to claim 1 further including an output capacitor coupled between said positive output node and said negative power node.
7. A circuit according to claim 1 wherein a frequency of switching of said power transistors is adjusted based on a load to said circuit.
8. A circuit according to claim 1 wherein signals produced by said first and second power transistors are 180 degrees out of phase from signals produced by said third and fourth power transistors.
9. A circuit according to claim 1 wherein a frequency of switching of said power transistors is adjusted when a duty cycle for said circuit is lower than 0.5.
10. A power factor correction AC/DC converter circuit comprising:
a full bridge diode rectifier subcircuit for receiving an input AC signal;
a first boost converter subcircuit;
a second boost converter subcircuit; and
a passive auxiliary subcircuit coupled between said first and second boost subcircuits, said passive auxiliary subcircuit being for providing reactive current to said boost converter subcircuits for zero voltage switching;
wherein
said first and second boost converter subcircuits are coupled in parallel to said rectifier subcircuit;
said passive auxiliary subcircuit comprises an auxiliary inductor and an auxiliary capacitor coupled in series to each other.
11. A circuit according to claim 10 wherein each boost converter subcircuit comprises:
a boost inductor;
a first boost power transistor; and
a second boost power transistor.
12. A circuit according to claim 11 wherein each end of said passive auxiliary subcircuit is coupled to a node between said first and second boost power transistor in one of said boost converter subcircuits.
13. A circuit according to claim 10 wherein signals produced by said first boost converter subcircuit are 180 degrees out of phase from signals produced by said second boost converter subcircuit.
14. A circuit according to claim 10 wherein a frequency of switching of said boost power transistors is adjusted based on a load to said circuit.