Semiconductor storage device and memory system

1. A semiconductor storage device, wherein the semiconductor storage device is configured to generate a third signal for latching data based on one of a first signal and a second signal, the first and second signals being output from an address change detection signal terminal which is configured to receive a signal indicating a change in the address signal, to set a first access mode for subsequent cycles based on a first pulse width of the first signal indicating a first address change, to set a second access mode for the subsequent cycles based on a second pulse width of the second signal indicating a second address change and to perform an access operation to a core circuit based on one of the first access mode and the second access mode which are set based on the first address change and the second address change, respectively,

wherein the first access mode is a synchronous operating mode, and the second access mode is an asynchronous operating mode,

wherein the address change detection signal terminal is provided in addition to an address input terminal to receive an address signal.

2. The semiconductor storage device according to claim 1 , wherein the first pulse width is different from the second pulse width, and a third a pulse width of the third signal is substantially constant regardless of the first pulse width and the second pulse width.

3. The semiconductor storage device according to claim 1 , wherein a fourth signal is generated in synchronization with a timing signal and one of the first access mode and the second access mode is set in synchronization with an access end signal indicating an end of access to the core circuit.

4. The semiconductor storage device according to claim 1 , wherein the first access mode and the second access mode are set when a column control signal is changed.