Scan test circuitry configured for bypassing selected segments of a multi-segment scan chain
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells, wherein the scan chain is separated into a plurality of scan segments with each such segment comprising a distinct subset of two or more of the plurality of scan cells. The scan test circuitry further comprises scan segment bypass circuitry configured to selectively bypass one or more of the scan segments in a scan shift mode of operation. The scan segment bypass circuitry may comprise a plurality of multiplexers and a scan segment bypass controller. The multiplexers are arranged within the scan chain and configured to allow respective ones of the scan segments to be bypassed responsive to respective bypass control signals generated by the scan segment bypass controller.
1. An integrated circuit comprising:
scan test circuitry; and
additional circuitry subject to testing utilizing the scan test circuitry;
the scan test circuitry comprising at least one scan chain having a plurality of scan cells;
wherein the scan chain is separated into a plurality of scan segments with each such segment comprising a distinct subset of two or more of the plurality of scan cells;
the scan test circuitry further comprising scan segment bypass circuitry configured to selectively bypass one or more of the scan segments in a scan shift mode of operation.
2. The integrated circuit of claim 1 wherein the scan segment bypass circuitry comprises:
a plurality of multiplexers arranged within the scan chain and configured to allow respective ones of the scan segments to be bypassed responsive to respective bypass control signals; and
a scan segment bypass controller configured to generate said bypass control signals for application to the multiplexers.
3. The integrated circuit of claim 2 wherein the plurality of multiplexers comprises a plurality of two-to-one multiplexers.
4. The integrated circuit of claim 2 wherein a given one of the multiplexers comprises:
a first input coupled to a scan input of a corresponding one of the scan segments;
a second input coupled to a scan output of the corresponding one of the scan segments;
an output coupled to a scan input of a subsequent scan segment of the scan chain; and
a select line adapted for receiving a bypass control signal for controlling the multiplexer between at least a first state in which the corresponding scan segment is not bypassed and a second state in which the corresponding scan segment is bypassed.
5. The integrated circuit of claim 2 wherein the scan segment bypass controller comprises a finite state machine.
6. The integrated circuit of claim 5 wherein the finite state machine comprises a plurality of states including a reset state in which none of the scan segments is bypassed and a plurality of additional states in which respective ones of the scan segments are bypassed.
7. The integrated circuit of claim 6 wherein the finite state machine is configured to cycle through the states responsive to a control signal from a control signal generator of the scan segment bypass controller.
8. The integrated circuit of claim 7 wherein the control signal is configured to cause the finite state machine to move from state to state only after application of at least one test pattern to the scan chain within a given such state.
9. The integrated circuit of claim 8 wherein at least two test patterns are applied within the given state before the state machine moves to a subsequent state.
10. The integrated circuit of claim 1 wherein each of a plurality of scan chains of the scan test circuitry is separated into scan segments in substantially the same manner.
11. The integrated circuit of claim 1 wherein the scan chain is separated into scan segments such that each of the scan segments of the scan chain has a length in scan cells that is less than or equal to a specified maximum segment length.
12. A processing device comprising the integrated circuit of claim 1 .
13. A method comprising:
configuring at least one scan chain to include a plurality of scan cells, the scan chain being separated into a plurality of scan segments with each such segment comprising a distinct subset of two or more of the plurality of scan cells; and
selectively bypassing one or more of the scan segments in a scan shift mode of operation.
14. The method of claim 13 wherein the step of selectively bypassing one or more of the scan segments comprises applying bypass control signals to respective multiplexers arranged within the scan chain and configured to allow respective ones of the scan segments to be bypassed.
15. The method of claim 14 wherein each of the multiplexers comprises a select line adapted for receiving a corresponding one of the bypass control signals for controlling the multiplexer between at least a first state in which the corresponding scan segment is not bypassed and a second state in which the corresponding scan segment is bypassed.
16. The method of claim 13 wherein the step of selectively bypassing one or more of the scan segments comprises bypassing said one or more segments under control of a finite state machine having a plurality of states including a reset state in which none of the scan segments is bypassed and a plurality of additional states in which respective ones of the scan segments are bypassed.
17. The method of claim 16 wherein the finite state machine is configured to cycle through the states responsive to a control signal.
18. The method of claim 17 wherein the control signal is configured to cause the finite state machine to move from state to state only after application of a particular number of test patterns to the scan chain within a given such state.
19. A computer program product comprising a non-transitory computer-readable storage medium having computer program code embodied therein for use in scan testing an integrated circuit, wherein the computer program code when executed in a testing system causes the testing system to perform the steps of the method of claim 13 .
20. A processing system comprising:
a processor; and
a memory coupled to the processor and configured to store information characterizing an integrated circuit design;
wherein the processing system is configured to provide scan test circuitry within the integrated circuit design, the scan test circuitry comprising at least one scan chain having a plurality of scan cells;
wherein the scan chain is separated into a plurality of scan segments with each such segment comprising a distinct subset of two or more of the plurality of scan cells;
the scan test circuitry further comprising scan segment bypass circuitry configured to selectively bypass one or more of the scan segments in a scan shift mode of operation.