IP Library Granted Patent US 8,729,595
Granted Patent B2
US 8,729,595 · App. 14/018,297 · Granted May 20, 2014

Light emitting device having vertical structure and package thereof

Inventors: Jun Ho Jang (Anyang-si, KR); Geun Ho Kim (Seoul, KR)
Assignees: LG Electronics Inc.; LG Innotek Co., Ltd.
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Quick Facts
Patent No.
US 8,729,595
App. No.
14/018,297
Granted
May 20, 2014
Kind
B2
Abstract

A light emitting device having a vertical structure and a package thereof, which are capable of damping impact generated in a substrate separation process, and achieving an improvement in mass productivity. The device and package include a sub-mount, a first-type electrode, a second-type electrode, a light emitting device, a zener diode, and a lens on the sub-mount.

Claims (37)

1. A light emitting device package comprising:

a sub-mount having a first surface and a second surface, the first surface includes a first portion and a second portion;

a first-type electrode and a second-type electrode on the first surface of the sub-mount;

a light emitting device on the first portion, the light emitting device comprising a supporting layer including an anti-diffusion layer, a first electrode and a second electrode on the supporting layer, and a semiconductor layer comprising a first conductive type semiconductor layer, a second conductive type semiconductor and an active layer between the first type semiconductor layer and the second type semiconductor layer;

a zener diode on the second portion of the sub-mount such that the zener diode is electrically connected to the first-type electrode and the second-type electrode; and

a lens on the sub-mount, the lens is disposed over the light emitting device,

wherein the first type semiconductor layer is electrically connected to the first electrode and the second type semiconductor layer is electrically connected to the second electrode,

wherein the first electrode is electrically connected to the first-type electrode and the second electrode is electrically connected to the second-type electrode,

wherein the light emitting device comprises a light extraction structure, and the zener diode is arranged a distance apart from the light emitting device,

wherein a horizontal cross-sectional area adjacent to the upper surface of the semiconductor layer is different from a horizontal cross-sectional area adjacent to a lower surface of the semiconductor layer, and

wherein the first electrode is disposed between the first conductive type semiconductor layer and the supporting layer, and the second electrode is disposed over the second conductive type semiconductor layer.

2. The device according to claim 1 , wherein at least a portion of a side surface of the supporting layer overlaps with a side surface of the first electrode horizontally.

3. The device according to claim 1 , wherein a height of the first portion is less than a height of the second portion.

4. The device according to claim 1 , wherein the first type semiconductor layer is a p-type GaN semiconductor layer and the second type semiconductor layer is an n-type GaN semiconductor layer.

5. The device according to claim 1 , wherein a polarity of the first electrode and a polarity of the second electrode are different from each other.

6. The device according to claim 1 , wherein the supporting layer surrounds the first electrode.

7. The device according to claim 1 , wherein the supporting layer is arranged between the first-type electrode and the second-type electrode.

8. The device according to claim 1 , wherein the supporting layer comprises a metal plate.

9. The device according to claim 8 , wherein the metal plate comprises at least one of Cu, Ni, Au, and an alloy thereof.

10. The device according to claim 1 , wherein the supporting layer comprises a semiconductor.

11. The device according to claim 1 , wherein the light extraction structure comprises at least one of an irregularity pattern, a photonic crystal, and a plurality of nano particles.

12. The device according to claim 1 , wherein the light extraction structure is an integral part of the semiconductor layer.

13. The device according to claim 1 , wherein the light extraction structure is arranged at a light emission surface of the semiconductor.

14. The device according to claim 1 , further comprising a passivation layer arranged on the semiconductor layer.

15. The device according to claim 1 , wherein the first electrode comprises at least two metals, or has a multilayer structure of at least two metal layers alternately arranged.

16. The device according to claim 1 , wherein the first electrode comprises an ohmic contact layer and a reflection electrode.

17. The device according to claim 1 , wherein the sub-mount comprises one of Si, AlN, ceramic, AlOx, Al2O3, BeO, and PCB.

18. The device according to claim 1 , wherein the sub-mount comprises one of a planar sub-mount, a 3D sub-mount, and a 3D through hole interconnection (THI) sub-mount.

19. The device according to claim 1 , wherein the sub-mount comprises a mount portion.

20. A light emitting device package comprising:

a sub-mount having a first surface and a second surface, the first surface includes a first portion and a second portion;

a first-type electrode and a second-type electrode on the first surface of the sub-mount;

a light emitting device on the first portion, the light emitting device comprising a first electrode and a second electrode on the supporting layer, and a semiconductor layer comprising a first conductive type semiconductor layer, a second conductive type semiconductor and an active layer between the first type semiconductor layer and the second type semiconductor layer; and

a zener diode on the second portion,

wherein the light emitting device comprises a light extraction structure, the zener diode is arranged a distance apart from the light emitting device, and the supporting layer surround the first electrode,

wherein a horizontal cross-sectional area adjacent to the upper surface of the semiconductor layer is different from a horizontal cross-sectional area adjacent to the lower surface of the semiconductor layer, and

wherein the first electrode is disposed between the first conductive type semiconductor layer and the supporting layer, and the second electrode is disposed over the second conductive type semiconductor layer.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 25, 2025
From: LG ELECTRONICS INC.
To: SUZHOU LEKIN SEMICONDUCTOR CO., LTD.
Reel/Frame 072529/0173 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2021
From: LG INNOTEK CO., LTD.
To: SUZHOU LEKIN SEMICONDUCTOR CO., LTD.
Reel/Frame 056366/0335 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 5, 2013
From: JANG, JUN HO; KIM, GEUN HO
To: LG ELECTRONICS INC.; LG INNOTEK CO., LTD.
Reel/Frame 031139/0602 →
Priority Claims (2)
KR 10-2006-0015039 · Feb 16, 2006 · national
KR 10-2006-0015040 · Feb 16, 2006 · national
Continuity (3)
Continuation 13080764 · Apr 6, 2011
Continuation 11701535 · Feb 2, 2007
Related Publication 20140021482A1 · Jan 23, 2014