Memory system

1. A memory system comprising:

a first semiconductor memory which receives a first clock, and outputs, in accordance with the first clock, a second clock and a data signal in synchronization with the second clock; and

a controller comprising a detection circuit which detects a shift of a duty ratio of the second clock which is output from the first semiconductor memory, and also comprising an adjustment circuit which adjusts a duty ratio of the first clock based on the shift detected by the detection circuit,

wherein when the first semiconductor memory and the controller are turned on, the duty ratio of a first pulse of the first clock which is output from the controller is different from the duty ratio of a second pulse of the first clock which is output after the first pulse of the first clock.

2. The memory system according to claim 1 ,

wherein the first semiconductor memory comprises a storage unit which stores information about the shift of the duty ratio of the second clock, and

the adjustment circuit adjusts the duty ratio of the first clock, based on the information stored in the storage unit.

3. The memory system according to claim 2 ,

wherein the storage unit comprises any one of a ROM fuse and a register.

4. The memory system according to claim 1 ,

wherein the adjustment circuit adjusts the duty ratio of the first clock so that a ratio between a high level period and a low level period of the second clock becomes close to 50:50.

5. The memory system according to claim 1 ,

wherein the first semiconductor memory outputs the second clock and the data signal in accordance with rising and falling edges of the first clock.

6. The memory system according to claim 1 ,

wherein the first semiconductor memory includes a NAND flash memory.

7. A memory system comprising:

a first semiconductor memory which receives a first clock, and outputs, in accordance with the first clock, a second clock and a data signal in synchronization with the second clock;

a second semiconductor memory which receives a third clock, and outputs, in accordance with the third clock, a fourth clock and a data signal in synchronization with the fourth clock; and

a controller comprising a detection circuit which detects a shift of a duty ratio of each of the second and fourth clocks which are output from the first and second semiconductor memories, and also comprising an adjustment circuit which adjusts duty ratios of the first and third clocks based on the amounts of shift detected by the detection circuit,

wherein when the first and second semiconductor memories and the controller are turned on, the duty ratios of first pulses of the first and third clocks which are output from the controller are different from the duty ratios of second pulses of the first and third clocks which are output after the first pulses of the first and third clocks.

8. The memory system according to claim 7 ,

wherein the first semiconductor memory comprises a first storage unit which stores information about the shift of the duty ratio of the second clock,

the second semiconductor memory comprises a second storage unit which stores information about the shift of the duty ratio of the fourth clock

the adjustment circuit adjusts the duty ratios of the first and third clocks, based on the information stored in the first and second storage units.

9. The memory system according to claim 8 ,

wherein the first and second storage units comprise any one of a ROM fuse and a register.

10. The memory system according to claim 7 ,

wherein the duty ratio of the first clock which is output from the controller to the first semiconductor memory is different from the duty ratio of the third clock which is output from the controller to the second semiconductor memory.

11. The memory system according to claim 7 ,

wherein the adjustment circuit adjusts the duty ratio of the first clock so that a ratio between a high level period and a low level period of the second clock becomes close to 50:50.

12. The memory system according to claim 11 ,

wherein the adjustment circuit adjusts the duty ratio of the third clock so that a ratio between a high level period and a low level period of the fourth clock becomes close to 50:50.

13. The memory system according to claim 7 ,

wherein the first and second semiconductor memories include NAND flash memories.

14. A memory system comprising:

a semiconductor memory comprising a storage unit storing information; and

a controller which controls operation of the semiconductor memory, and reads data from the semiconductor memory,

wherein when the semiconductor memory and the controller are turned on, the controller reads the information stored in the storage unit in the semiconductor memory,

wherein the semiconductor memory receives a first clock, and outputs, in accordance with the first clock, a second clock and a data signal in synchronization with the second clock,

the information stored in the storage unit indicates the shift of the duty ratio of the second clock,

the controller comprises an adjustment circuit which adjusts a duty ratio of the first clock based on the shift, and

when the semiconductor memory and the controller are turned on, the duty ratio of a first pulse of the first clock which is output from the controller is different from the duty ratio of a second pulse of the first clock which is output after the first pulse of the first clock.

15. The memory system according to claim 14 ,

wherein the adjustment circuit adjusts the duty ratio of the first clock so that a ratio between a high level period and a low level period of the second clock becomes close to 50:50.

16. The memory system according to claim 14 ,

wherein the semiconductor memory outputs the second clock and the data signal in accordance with rising and falling edges of the first clock.

17. The memory system according to claim 1 ,

wherein immediately after the first semiconductor memory and the controller are turned on, the first clock which is output from the controller comprises a duty ratio different in terms of time series.