Semiconductor device having a through contact and a manufacturing method therefor

1. A method of forming a semiconductor device, comprising:

providing a wafer comprising:

a semiconductor substrate having a first side and a second side opposite the first side; and

a dielectric region on the first side;

forming a further dielectric region on the first side;

mounting the wafer with the first side on a carrier system;

etching a deep vertical trench from the second side through the semiconductor substrate to the dielectric region, thereby insulating a semiconductor mesa region from the remaining semiconductor substrate;

etching a separation trench through the semiconductor substrate at least close to the further dielectric region;

masking the separation trench; and

filling the deep vertical trench with a dielectric material after masking the separation trench.

2. The method of claim 1 , wherein mounting the wafer with the first side on a carrier system comprises attaching the wafer to a glass substrate.

3. The method of claim 1 , further comprising prior to mounting the wafer at least one of:

forming a transistor structure in the semiconductor substrate;

forming a gate electrode structure on the first side;

forming a trench gate electrode structure extending form the first side into the semiconductor substrate; and

forming a field plate below the gate electrode structure or the trench the gate electrode structure.

4. The method of claim 1 , further comprising at least one of:

forming on the second side a metallization in low resistive contact with a gate electrode of a gate electrode structure or a trench gate electrode structure through the semiconductor mesa region;

forming on the second side an additional metallization in low resistive contact with a semiconductor body; and,

forming a dielectric structure on the filled deep vertical trench and between the metallizations.

5. The method of claim 1 , further comprising prior to mounting the wafer at least one of:

forming a contact layer in ohmic contact with the semiconductor mesa region on the first side;

forming a first metallization on the further dielectric region; and

structuring the first metallization.

6. The method of claim 1 , further comprising processing the second side to thin the semiconductor substrate prior to etching the deep vertical trench.

7. The method of claim 6 , wherein processing the second side comprises at least one of polishing, etching, grinding, and a CMP process.

8. The method of claim 1 , wherein filling the deep vertical trench with a dielectric material comprises at least one of forming a dielectric layer at least on a sidewall of the deep vertical trench, depositing a polymer, back etching the deposited polymer and a chemical-mechanical polishing process.

9. The method of claim 8 , wherein the dielectric layer is formed as a conformal dielectric layer.

10. The method of claim 1 , further comprising separating the wafer along the separation trench.

11. The method of claim 10 , wherein separating the wafer along the separation trench comprises at least one of mechanical breaking, laser cutting, and plasma etching.

12. A method of forming a plurality semiconductor devices, comprising:

providing a wafer comprising a semiconductor substrate comprising a plurality of semiconductor structures;

forming a first metallization for the plurality of semiconductor structures on the wafer;

mounting the wafer on a carrier system so that the first metallization is covered by the carrier system;

forming separation trenches through the semiconductor substrate of the mounted wafer and between the plurality of semiconductor structures together with at least one deep vertical trench;

filling the at least one deep vertical trench with a dielectric material while the separation trenches are masked, thereby forming at least one laterally insulated semiconductor mesa region; and

separating the plurality of semiconductor structures along the separation trenches.

13. The method of claim 12 , wherein forming the separation trenches comprises plasma etching.

14. The method of claim 12 , further comprising forming a control metallization in low resistive contact with the at least one laterally insulated semiconductor mesa region and arranged opposite the first metallization.

15. A method of forming a semiconductor device, comprising:

providing a semiconductor substrate comprising a first side and a second side opposite the first side;

defining an active area and a through contact area;

forming a recess from the first side into the semiconductor substrate such that the recess comprises in the through contact area a horizontally widening portion;

forming a first dielectric layer on the recess;

opening the first dielectric layer in the through contact area;

mounting the semiconductor substrate with the first side on a carrier system;

etching in the through contact area from the second side two deep circumferential vertical trenches through the semiconductor substrate to the first dielectric layer; and

insulating at least the sidewalls of the two deep circumferential vertical trenches to form a laterally insulated semiconductor mesa.

16. The method of claim 15 , wherein the recess is formed by masked etching such that the recess extends in the active area to a first vertical depth and in the through contact area to a second vertical depth which is larger than the first vertical depth.

17. The method of claim 15 , further comprising forming a conformal layer of a conductive material in the recess so that the recess is completely filled in the active area.

18. The method of claim 17 , further comprising back-etching the conformal layer to form a field electrode in the active area.

19. The method of claim 18 , further comprising at least one of forming a second dielectric layer on the field electrode, depositing a conductive material on the recess in ohmic contact with the semiconductor mesa, back-etching of the conductive material to form a gate electrode, and forming a control metallization on the second side in ohmic contact with the semiconductor mesa and the gate electrode.