Method and apparatus to limit memory power
In one embodiment, the present invention includes a power manager to receive a memory power usage value, to determine an available power based at least in part on a power budget and the memory power usage value, and to change a memory power state based at least in part on the available power, wherein the memory power state comprises a memory frequency and a memory voltage. Other embodiments are described and claimed.
1. A non-transitory storage medium comprising content which, when executed by an accessing machine, causes the accessing machine to:
receive a power value that is determined based on P states that represent a plurality of voltage and frequency level combinations to which a processor may be set, H states that represent a plurality of voltage and frequency level combinations to which ranks within a memory may be set and T states that represent a plurality of energy efficiency levels that throttle functionality of the memory and the processor;
determine an available power based at least in part on a power budget and the power value; and
change a memory power state based at least in part on the available power and the power value, wherein the memory power state comprises a memory frequency and a memory voltage by placing only a portion of memory into self refresh.
2. The storage medium of claim 1 , wherein the content to determine an available power based at least in part on a power budget and the memory power usage value comprises content to implement a running average power limit (RAPL).
3. The storage medium of claim 1 , further comprising content which, when executed by an accessing machine, causes the accessing machine to change memory timing settings.
4. The storage medium of claim 1 , further comprising content which, when executed by an accessing machine, causes the accessing machine to change a socket power state which coordinates the memory power state with a processor power state.
5. The storage medium of claim 1 , further comprising content which, when executed by an accessing machine, causes the accessing machine to receive a system power usage value.
6. The storage medium of claim 5 , further comprising content which, when executed by an accessing machine, causes the accessing machine to change a processor power state.
7. The storage medium of claim 5 , wherein the content to receive a system power usage value comprises content to receive calibrated weight estimations.
8. A system comprising:
a processor including a memory controller;
a dynamic random access memory (DRAM) coupled to the processor; and
a power manager to receive a power value that is determined based on P states that represent a plurality of voltage and frequency level combinations to which a processor may be set, H states that represent a plurality of voltage and frequency level combinations to which ranks within a memory may be set and T states that represent a plurality of energy efficiency levels that throttle functionality of the memory and the processor, to determine an available power based at least in part on a power budget and the power value, and to change a memory power state based at least in part on the available power and the power value, wherein the memory power state comprises a memory frequency and a memory voltage by placing only a portion of memory into self refresh.
9. The system of claim 8 , wherein the power manager to determine an available power based at least in part on a power budget and the memory power usage value comprises the power manager to implement a running average power limit (RAPL).
10. The system of claim 8 , further comprising the power manager to change memory timing settings.
11. The system of claim 10 , wherein the power manager to change memory timing settings comprises the power manager to change column access strobe (CAS) timings.
12. The system of claim 8 , further comprising the power manager to change a processor power state.
13. A method comprising:
receiving a power value that is determined based on P states that represent a plurality of voltage and frequency level combinations to which a processor may be set, H states that represent a plurality of voltage and frequency level combinations to which ranks within a memory may be set and T states that represent a plurality of energy efficiency levels that throttle functionality of the memory and the processor;
determining an available power based at least in part on a power budget and the power value; and
changing a memory power state based at least in part on the available power and the power value, wherein the memory power state comprises a memory frequency and a memory voltage by placing only a portion of memory into self refresh.
14. The method of claim 13 , further comprising changing memory timing settings.
15. The method of claim 13 , wherein changing memory timing settings comprises changing column access strobe (CAS) timings.
16. The method of claim 13 , further comprising receiving a silicon power usage value.
17. The method of claim 16 , further comprising changing a processor power state.
18. The method of claim 16 , receiving a silicon power usage value comprises receiving calibrated weight estimations.