Semiconductor device and method for manufacturing semiconductor device
Disclosed herein are a semiconductor device, and a method for manufacturing the semiconductor device. The semiconductor device includes a semiconductor substrate, a base region formed on an upper region of an inside of the semiconductor substrate, at least one gate electrode that penetrates through the base region and has an inverted triangular shape, a gate insulating film formed to enclose an upper portion of the semiconductor substrate and the gate electrode, an inter-layer insulating film formed on an upper portion of the gate electrode and the gate insulating film, an emitter region formed inside the base region and on both sides of the gate electrode, an emitter metal layer formed on an upper portion of the base region and inter-layer insulating film, and a buffer region formed to enclose a lower portion of the gate electrode and to be spaced apart from the base region.
1. A semiconductor device comprising:
a semiconductor substrate;
a base region that is formed on an upper region of an inside of the semiconductor substrate;
at least one gate electrode that penetrates through the base region and is formed into an inverted triangular shape;
a gate insulating film that is formed so as to enclose an upper portion of the semiconductor substrate and the gate electrode;
an inter-layer insulating film that is formed on an upper portion of the gate electrode and the gate insulating film;
an emitter region that is formed inside the base region and on both sides of the gate electrode;
an emitter metal layer that is formed on an upper portion of the base region and on an upper portion of the inter-layer insulating film; and
a buffer region that is formed so as to enclose a lower portion of the gate electrode and formed so as to be spaced apart from the base region.
2. The semiconductor device as set forth in claim 1 , wherein the semiconductor substrate is an N-type semiconductor substrate.
3. The semiconductor device as set forth in claim 1 , wherein the base region includes P-type low concentration impurities.
4. The semiconductor device as set forth in claim 1 , wherein the emitter region includes N-type high concentration impurities.
5. The semiconductor device as set forth in claim 1 , wherein the buffer region includes P-type high concentration impurities.
6. The semiconductor device as set forth in claim 1 , wherein the gate insulating film includes at least one of a silicon oxide layer, silicon oxynitride (SiON), germanium oxynitride (GexOyNz), and a high dielectric constant material.
7. The semiconductor device as set forth in claim 1 , wherein the gate electrode is formed of polysilicon.
8. The semiconductor device as set forth in claim 1 , wherein the inter-layer insulating film includes at least one of borophosphosilicate glass (BPSG) and tetraethylorthosilicate (TEOS).
9. The semiconductor device as set forth in claim 1 , wherein the semiconductor substrate is a <100> type silicon wafer.
10. A method for manufacturing a semiconductor device comprising:
preparing a semiconductor substrate;
forming an inverted triangular-shaped gate trench on the semiconductor substrate;
forming a buffer region that encloses a lower portion of the gate trench;
forming a gate insulating film on an upper portion of the semiconductor substrate and an inner wall of the gate trench;
forming a gate electrode inside the gate trench;
forming an inter-layer insulating film on an upper portion of the gate electrode;
forming a base region on an upper portion of an inside of the semiconductor substrate so as to be spaced apart from the buffer region;
forming an emitter region inside the base region and on both sides of the gate electrode; and
forming an emitter metal layer on an upper portion of the base region and on an upper portion of the inter-layer insulating film.
11. The method for manufacturing the semiconductor device as set forth in claim 10 , wherein the semiconductor substrate is an N-type semiconductor substrate.
12. The method for manufacturing the semiconductor device as set forth in claim 10 , wherein the semiconductor substrate is a <100> type silicon wafer.
13. The method for manufacturing the semiconductor device as set forth in claim 10 , wherein the forming of the gate trench includes:
forming a patterned etching resist on the upper portion of the semiconductor substrate,
forming the inverted triangular-shaped gate trench by performing wet etching on the semiconductor substrate, and
removing the etching resist.
14. The method for manufacturing the semiconductor device as set forth in claim 10 , wherein, in the forming of the buffer region, the buffer region is formed by injecting P-type high concentration impurities into the semiconductor substrate through the gate trench.
15. The method for manufacturing the semiconductor device as set forth in claim 10 , wherein, in the forming of the gate insulating film, the gate insulating film includes at least one of a silicon oxide layer, silicon oxynitride (SiON), GexOyNz, and a high dielectric constant material.
16. The method for manufacturing the semiconductor device as set forth in claim 10 , wherein the forming of the gate electrode includes:
forming a polysilicon that is formed inside the gate trench, on an upper portion of the gate trench, and on an upper portion of the gate insulating film, and
removing the polysilicon formed on the upper portion of the gate trench and the upper portion of the gate insulating film by an etch back or wet etching process.
17. The method for manufacturing the semiconductor device as set forth in claim 10 , wherein, in the forming of the inter-layer insulating film, the inter-layer insulating film includes at least one of borophosphosilicate glass (BPSG) and tetraethylorthosilicate (TEOS).
18. The method for manufacturing the semiconductor device as set forth in claim 10 , wherein, in the forming of the base region, the base region is formed by injecting P-type low concentration impurities into the semiconductor substrate.
19. The method for manufacturing the semiconductor device as set forth in claim 10 , wherein, in the forming of the emitter region, the emitter region is formed by injecting N-type high concentration impurities into the base region.