Output device
An output device receives a data signal, outputs an output signal corresponding to the data signal in synchronization with a clock signal, and includes a driving unit configured to drive an output buffer that outputs the output signal. The driving unit includes a signal switching unit and first and second driving circuits that operate with the same power supply. The signal switching unit inputs the clock signal into one of the first and second driving circuits in accordance with the level of the data signal, and the one of the first and second driving circuits outputs a driving signal whose level varies in accordance with a change in the level of the clock signal to the output buffer.
1. A output device, comprising:
an output buffer including a first buffer switch connected between a first supply voltage and an output terminal that outputs an output signal and a second buffer switch connected between the output terminal and a second supply voltage;
a driving unit that receives a clock signal and a data signal and drives the output buffer in synchronization with the clock signal, the driving unit including:
a first and a second driving circuit that operate with the same power supply, the first and second driving circuit driving the first and second buffer switches, respectively; and
a signal, switching device that selects one of the first and second driving circuits in accordance with a logical level of the data signal and supplies a selection signal to the selected one of the driving circuits, the selection signal having a selection signal level that changes in synchronization with a change of a logical level of the clock signal,
wherein the selected one of the first and second driving circuits outputs a driving signal having a driving signal level that changes in synchronization with the logical level of the clock signal to a corresponding one of the first and second buffer switches.
2. The output device of claim 1 , wherein:
the selected one of the first and second driving circuits output the driving signal having the driving signal level to the corresponding one of the first and second buffer switches, and the other one of the first and second driving circuits outputs a keeping signal having a fixed level that keeps the other one of the first and second buffer switches off to the other one of the buffer switches.
3. The output device of claim 2 , wherein:
the signal switching device includes a pair of a differential amplifiers each receiving the clock signal and a inverted signal of the clock signal and a selection switch that selects one of the pair of differential amplifiers in accordance with the logical level of the data signal so that the selected one of the differential amplifiers outputs the selection signal.
4. A semiconductor integrated circuit comprising a plurality of the output devices of claim 1 , wherein:
the first and second driving circuits in the plurality of output devices operate with the same power supply.
5. A semiconductor integrated circuit comprising a plurality of the output devices of claim 4 , wherein:
in each of the plurality of output devices, the selected one of the first and second driving circuits output the driving signal having the driving signal level to the corresponding one of the first and second butler switches, and the other one of the first and second driving circuits outputs a keeping signal having a fixed level that keeps the other one of the first and second buffer switches off to the other one of the buffer switches.
6. A semiconductor integrated circuit comprising:
a plurality of output devices, each comprising,
an output buffer including a first buffer switch connected between a first supply voltage and an output terminal that outputs an output signal and a second buffer switch connected between the output terminal and a second supply voltage;
a driving unit that receives a clock signal and a data signal and drives the output buffer in synchronization with the clock signal, the driving unit including:
a first and a second driving circuit, the first and second driving circuit driving the first and second buffer switches, respectively; and
a signal switching device that selects one of the first and second driving circuits in accordance with a logical level of the data signal and supplies a selection signal to the selected one of the driving circuits, the selection signal having a selection signal level that changes in synchronization with a change of a logical level of the clock signal; and
a current generator that generates a fixed output current when the output signal has a first logical level;
wherein the selected one of the first and second driving circuits outputs a driving signal having a driving signal level that changes in synchronization with the logical level of the clock signal to a corresponding one of the first and second buffer switches; and
a summing circuit that sums the output current generated by each of the plurality of output devices to generate a summed output signal;
wherein the first and second driving circuits in the plurality of output devices operate with the same power supply.
7. The semiconductor integrated circuit of claim 6 , wherein:
in each of the plurality of output devices, the selected one of the first and second driving circuits output the driving signal having the driving signal level to the corresponding one of the first and second buffer switches, and the other one of the first and second driving circuits outputs a keeping signal having a fixed level that keeps the other one of the first and second buffer switches off to the other one of the buffer switches.
8. A digital-to-analog converter comprising:
a plurality of output devices, each comprising,
an output buffer including a first buffer switch connected between a first supply voltage and an output terminal that outputs an output signal and a second buffer switch connected between the output terminal and a second supply voltage;
a driving unit that receives a clock signal and a data signal and drives the output buffer in synchronization with the clock signal, the driving unit including:
a first and a second driving circuit, the first and second driving circuit driving the first and second buffer switches, respectively;
a signal switching device that selects one of the first and second driving circuits in accordance with a logical level of the data signal and supplies a selection signal to the selected one of the driving circuits, the selection signal having a selection signal level that changes in synchronization with a change of a logical level of the clock signal; and
a current generator that generates a fixed output current when the output signal has a first logical level;
wherein the selected one of the first and second driving circuits outputs a driving signal having a driving signal level that changes in synchronization with the logical level of the clock signal to a corresponding one of the first and second buffer switches; and
a decoder that receives a digital input signal and converts the digital input signal to the data signal to be supplied to each of the plurality of output devices; and
a summing circuit that sums the output current generated by each of the plurality of output devices to generate an analog output signal corresponding to the input digital signal;
wherein the first and second driving circuits in the plurality of output devices operate with the same power supply.
9. The digital-to-analog converter of claim 8 , wherein;
in each of the plurality of output devices, the selected one of the first and second driving circuits output the driving signal having the driving signal level to the corresponding one of the first and second buffer switches, and the other one of the first and second driving circuits outputs a keeping signal having a fixed level that keeps the other one of the first and second buffer switches off to the other one of the buffer switches.