Multi-stack semiconductor integrated circuit device
The invention relates to a multi-stack semiconductor integrated circuit device where communication between semiconductor chips can be efficiently carried out by bypassing a number of chips. Each semiconductor chip that forms a multi-stack semiconductor integrated circuit device having a stack structure where four or more semiconductor chips having the same shape are stacked on top of each other is provided with: a first coil for transmission/reception for communication between chips over a long distance; and a second coil for transmission/reception for communication between chips over a short distance, of which the size is smaller than that of the above-described first coil for transmission/reception.
1. A multi-stack semiconductor integrated circuit device having a stack structure comprising:
four or more semiconductor chips having the same shape and being stacked on top of each other, wherein each semiconductor chip comprises:
a first coil for transmission/reception for communication between chips over a long distance; and
a second coil for transmission/reception for communication between chips over a short distance, of which the size is smaller than that of said first coil for transmission/reception
wherein a semiconductor chip, of which the size is smaller than that of said semiconductor chips and which has a different shape and only a third coil for transmission/reception for communication between chips having the same size as that of said second coil for transmission/reception, is stacked on the top or bottom semiconductor chip in said stack structure.
2. The multi-stack semiconductor integrated circuit device according to claim 1 , wherein
said first coil for transmission/reception and said second coil for transmission/reception are polygonal, and
the diameter of the circle that inscribes said first coil for transmission/reception and said second coil for transmission/reception is 1 to 3 times greater than the distance for communication between chips that has been set in accordance with the size of the coils.
3. The multi-stack semiconductor integrated circuit device according to claim 2 , wherein the diameter of the circle that inscribes said first coil for transmission/reception is 4 to 36 times greater than the pitch at which said semiconductor chips are stacked on top of each other.
4. The multi-stack semiconductor integrated circuit device according to claim 1 , wherein said multi-stack structure comprises at least:
a first semiconductor chip group where a predetermined number of semiconductor chips are stacked on top of each other in such a manner that a first pair of sides of each semiconductor chip is aligned with that of the semiconductor chip at the bottom, and a second pair of sides of each semiconductor chip is shifted by a predetermined pitch sequentially in a first direction in which said first pair of sides runs;
a second semiconductor chip group where a predetermined number of semiconductor chips are stacked on top of each other in such a manner that a second pair of sides of each semiconductor chip is aligned with the second pair of the semiconductor chip at the top of said first semiconductor chip group, and a first pair of sides of each semiconductor chip is shifted by a predetermined pitch sequentially in a second direction in which said second pair of sides runs;
a third semiconductor chip group where the same number of semiconductor chips as in the first semiconductor chip group are stacked on top of each other in such a manner that a first pair of sides of each semiconductor chip is aligned with the first pair of sides of the semiconductor chip at the top of said second semiconductor chip group, and a second pair of sides of each semiconductor chip is shifted by a predetermined pitch sequentially in a third direction that is opposite to said first direction; and
a fourth semiconductor chip group where the same number of semiconductor chips as in said second semiconductor chip group are stacked on top of each other in such a manner that a second pair of sides of each semiconductor chip is aligned with the second pair of the semiconductor chip at the top of said third semiconductor chip group, and a first pair of sides of each semiconductor chip is shifted by a predetermined pitch sequentially in a fourth direction that is opposite to said second direction.
5. The multi-stack semiconductor integrated circuit device according to claim 1 , wherein said semiconductor chips having the same shape are flash memory chips and said semiconductor chip having a different shape is a controller chip for controlling the operation of said flash memories.