IP Library Granted Patent US 8,748,321
Granted Patent B2
US 8,748,321 · App. 13/901,767 · Granted Jun 10, 2014

Method for epitaxial devices

Inventors: Anton deVilliers (Boise, ID); Erik Byers (Boise, ID); Scott E. Sills (Boise, ID)
Assignee: Micron Technology, Inc.
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Quick Facts
Patent No.
US 8,748,321
App. No.
13/901,767
Granted
Jun 10, 2014
Kind
B2
Abstract

Epitaxial growth methods and devices are described that include a textured surface on a substrate. Geometry of the textured surface provides a reduced lattice mismatch between an epitaxial material and the substrate. Devices formed by the methods described exhibit better interfacial adhesion and lower defect density than devices formed without texture. Silicon substrates are shown with gallium nitride epitaxial growth and devices such as LEDs are formed within the gallium nitride.

Claims (23)

1. A method of forming a light emitting diode device, comprising:

applying a block copolymer to a silicon surface;

organizing the block copolymer into a substantially regular pattern;

selectively etching the silicon surface of using the regular pattern of the organized block copolymer as a mask to form a corresponding textured surface of the substrate;

forming epitaxial gallium nitride on the textured surface, wherein a geometry of the textured surface reduces a lattice mismatch between the epitaxial gallium nitride and the silicon surface; and

forming a P-N junction within the gallium nitride to provide a desired wavelength of light.

2. The method of claim 1 , wherein selectively etching the silicon surface includes forming the textured surface so that a periodicity of the texture corresponds to a value within approximately +/−25% of an integer multiple of the lattice constant of the epitaxial gallium nitride.

3. The method of claim 1 , wherein selectively etching the silicon surface includes forming the textured surface to include a number of regularly spaced pyramidal structures.

4. The method of claim 1 , wherein selectively etching the silicon surface includes forming the textured surface to include a number of regularly spaced conical-shaped structures.

5. The method of claim 1 , wherein selectively etching the silicon surface includes forming the textured surface to include a number of asymmetric angled surfaces.

6. A method of forming a light emitting diode device, comprising:

applying a block copolymer to a semiconductor surface;

organizing the block copolymer into a substantially regular pattern;

selectively etching the semiconductor surface using the regular pattern of the organized block copolymer as a mask to form one or more angled surfaces within the semiconductor surface;

forming an epitaxial material on the one or more angled surfaces; and

forming a P-N junction within the epitaxial material to provide a desired wavelength of light.

7. The method of claim 6 , wherein applying a block copolymer to the semiconductor surface includes applying a di-block copolymer.

8. The method of claim 6 , wherein applying a block copolymer to the semiconductor surface includes applying a tri-block copolymer.

9. The method of claim 6 , wherein applying a block copolymer to the semiconductor surface includes applying a block copolymer to a silicon surface.

10. The method of claim 6 , wherein forming the epitaxial material on the one or more angled surfaces includes forming epitaxial gallium nitride on the one or more angled surfaces.

11. The method of claim 6 , wherein selectively etching the semiconductor surface includes forming the textured surface to include a number of regularly spaced pyramidal structures.

12. The method of claim 6 , wherein selectively etching the semiconductor surface includes forming the textured surface to include a number of regularly spaced conical-shaped structures.

13. The method of claim 6 , wherein selectively etching the semiconductor surface includes forming the textured surface to include a number of asymmetric angled surfaces.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 30, 2014
From: DEVILLIERS, ANTON; BYERS, ERIK; SILLS, SCOTT E.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032790/0440 →
Continuity (3)
Continuation 13528574 · Jun 20, 2012
Division 12826275 · Jun 29, 2010
Related Publication 20130256692A1 · Oct 3, 2013