Method of fabricating semiconductor device

1. A method of fabricating a semiconductor device, the method comprising:

forming a first interlayer dielectric (ILD) layer over a semiconductor substrate;

forming a first etch stop layer over the first ILD layer;

forming first contacts within the first ILD layer and the first etch stop layer;

forming a second etch stop layer over the first contacts and the first etch stop layer;

forming a second ILD layer over the second etch stop layer;

forming first trenches in the second ILD layer to expose the first contacts, by removing a portion of the second ILD layer, a portion of the second etch stop layer, and a portion of the first etch stop layer;

depositing a first metal layer to partially fill the first trenches, the first metal layer engaging the exposed first contacts;

depositing a dielectric material over the first metal layer in the first trenches; and

depositing a second metal layer over the dielectric material in the first trenches.

2. The method of claim 1 , wherein said removing the portion of the first etch stop layer to expose the first contacts is terminated without exposing the first ILD layer.

3. The method of claim 1 , wherein the first metal layer covers an entire inner surface of the first trenches.

4. The method of claim 1 , wherein the first metal layer directly contacts the first etch stop layer in the first trenches.

5. The method of claim 1 , wherein at least one of said depositing the first metal layer or said depositing the second metal layer comprises depositing TiN to a thickness ranging from about 100 to about 500 Å.

6. The method of claim 1 , wherein said depositing the dielectric material over the first metal layer comprises depositing ZrO 2 to a thickness ranging from about 50 to about 400 Å.

7. A method of fabricating a semiconductor device, the method comprising:

forming a silicide layer on first and second regions of a semiconductor substrate, the first region including an isolation structure, the second region including a doped region and a gate electrode;

forming a first interlayer dielectric (ILD) layer over the first region and over the second region;

forming a first etch stop layer over the first ILD layer;

forming first contacts within the first ILD layer and the first etch stop layer;

forming a second etch stop layer over the first contacts and the first etch stop layer;

forming a second ILD layer over the second etch stop layer;

forming first trenches in the second ILD layer to expose the first contacts, by removing a portion of the second ILD layer, a portion of the second etch stop layer, and a portion of the first etch stop layer;

depositing a first metal layer to partially fill the first trenches, the first metal layer engaging the exposed first contacts;

depositing a dielectric material over the first metal layer in the first trenches; and

depositing a second metal layer over the dielectric material in the first trenches.

8. The method of claim 7 , wherein said removing the portion of the first etch stop layer to expose the first contacts is terminated without exposing the first ILD layer.

9. The method of claim 7 , wherein the first metal layer covers an entire inner surface of the first trenches.

10. The method of claim 7 , wherein the first metal layer directly contacts the first etch stop layer in the first trenches.

11. The method of claim 7 , wherein at least one of said depositing the first metal layer or said depositing the second metal layer comprises depositing TiN to a thickness ranging from about 100 to about 500 Å.

12. The method of claim 7 , wherein said depositing the dielectric material over the first metal layer comprises depositing ZrO 2 to a thickness ranging from about 50 to about 400 Å.

13. The method of claim 7 , further comprising:

forming a memory cell, the memory cell including the first metal layer, the dielectric material, and the second metal layer.

14. A method of fabricating a semiconductor device, the method comprising:

forming a first insulating layer over a semiconductor substrate;

forming a contact plug within the first insulating layer;

forming an etch stop layer over the first insulating layer;

forming a second insulating layer over the etch stop layer, the second insulating layer having a contact opening over the contact plug, the contact opening further extending into a partial thickness of the etch stop layer;

depositing a first metal layer to partially fill the contact opening, the first metal layer engaging the contact plug and being free of direct contact with the first insulating layer;

depositing a dielectric material over the first metal layer in the contact opening; and

depositing a second metal layer over the dielectric material in the contact opening.

15. The method of claim 14 , wherein the first metal layer covers an entire inner surface of the contact opening.

16. The method of claim 14 , wherein the first metal layer directly contacts the etch stop layer in the contact opening.

17. The method of claim 14 , wherein at least one of said depositing the first metal layer or said depositing the second metal layer comprises depositing TiN to a thickness ranging from about 100 to about 500 Å.

18. The method of claim 14 , wherein said depositing the dielectric material over the first metal layer comprises depositing ZrO 2 to a thickness ranging from about 50 to about 400 Å.

19. The method of claim 14 , wherein

the contact plug comprises a sidewall extending downward from an upper portion to a lower portion of the contact plug; and

the first metal layer is free of direct contact with the sidewall of the contact plug.

20. The method of claim 14 , further comprising:

forming a further etch stop layer over the second insulating layer; and

forming a third insulating layer over the further etch stop layer;

wherein the contact opening extends through the third insulating layer, the further etch stop layer, and the second insulating layer.