Package and fabrication method of the same

1. A package comprising:

a conductive base plate including

a CTE (coefficient of thermal expansion) control layer configured to be composed of compound material, and

a heat conduction layer configured to be disposed on the CTE control layer and composed of Cu; wherein

the CTE control layer is composed of a first compound material and a second compound material, a mixing ratio of the first compound material is increased with nearing the heat conduction layer, and a mixing ratio of the second compound material is increased with distance away from the heat conduction layer, along a thickness direction of the CTE control layer, wherein

the mixing ratio between the first compound material and the second compound material in the CTE control layer is 20%/80% to 80%/20%, and the thickness of the CTE control layer is 0.4 mm to 0.8 mm.

2. The package according to claim 1 , wherein

the conductive base plate further comprises a thermal diffusion layer configured to intervene between the heat conduction layer and the CTE control layer.

3. The package according to claim 1 , wherein

the conductive base plate further comprises a thermal diffusion layer configured to be disposed on the heat conduction layer.

4. The package according to claim 1 , wherein the conductive base plate further comprises:

a first thermal diffusion layer configured to be disposed on the heat conduction layer; and

a second thermal diffusion layer configured to intervene between the heat conduction layer and the CTE control layer.

5. The package according to claim 2 , wherein

the thermal diffusion layer is one of a compound of a carbon fiber and Cu, a compound of a carbon fiber and Al, a compound of a diamond and Cu and, a compound of a diamond and Al.

6. The package according to claim 1 , wherein

the compound material is one of a compound of Cu and Mo, a compound of Cu and W, a compound of Al and Mo, and a compound of Al and W.

7. The package according to claim 1 , wherein the conductive base plate further comprises:

a contact thermal resistance reducing layer configured to be disposed on a bottom surface of the CTE control layer to oppose to the heat conduction layer.

8. The package according to claim 7 , wherein

the contact thermal resistance reducing layer is formed of Cu.

9. The package according to claim 1 further comprising:

a semiconductor device configured to be disposed on the conductive base plate;

a metal wall configured to be disposed on the conductive base plate to house the semiconductor device;

a through-hole configured to be disposed in input and output units of the metal wall;

a lower layer feed through configured to be inserted into the through-hole and disposed on the conductive base plate;

an upper layer feed through configured to be inserted into the through-hole and disposed on the lower layer feed through;

an input stripline configured to be disposed on the lower layer feed through in the input unit of the metal wall; and

an output stripline configured to be disposed on the lower layer feed through in the output unit of the metal wall.

10. The package according to claim 9 further comprising:

an input circuit substrate and an output circuit substrate configured be disposed, to adjoin of the semiconductor device, on the conductive base plate surrounded by the metal wall;

an input matching circuit configured to be disposed on the input circuit substrate and be connected to the input stripline;

an output matching circuit configured to be disposed on the output circuit substrate and be connected to the output stripline; and

a bonding wire configured to connect between the semiconductor device, and the input matching circuit and the output matching circuit.

11. The package according to claim 10 further comprising:

a metal seal ring configured to be disposed on the metal wall; and

a metal cap configured to be disposed on the metal seal ring.

12. The package according to claim 10 , wherein the semiconductor device comprises:

a semi-insulating substrate;

a gate finger electrode, a source finger electrode, and a drain finger electrode configured to be placed on a first surface of the semi-insulating substrate and to have a plurality of fingers, respectively;

a plurality of gate terminal electrodes, a plurality of source terminal electrodes, and a drain terminal electrode configured to be disposed on the first surface of the semi-insulating substrate and to tie a plurality of fingers, respectively for every the gate finger electrode, the source finger electrode, and the drain finger electrode;

a VIA hole configured to be disposed at an under part of the source terminal electrode; and

a ground electrode configured to be disposed on a second surface of the opposite side of the first surface of the semi-insulating substrate, and be connected via the VIA hole for the source terminal electrode.

13. The package according to claim 12 , wherein

the semi-insulating substrate is one of a GaAs substrate, an SiC substrate, a GaN substrate, a substrate formed of a GaN epitaxial layer on the SiC substrate, a substrate formed of a heterojunction epitaxial layer composed of GaN/AlGaN on the SiC substrate, a sapphire substrate, or a diamond substrate.