Apparatus for mixed signal interface acquisition circuitry and associated methods
An integrated circuit (IC) includes a plurality of pads adapted to communicate signals with a circuit external to the IC, and a first mixed signal interface block coupled to a first pad in the plurality of pads, where the first mixed signal interface block is adapted to receive a first trigger signal from the circuit external to the IC and to provide a second trigger signal. The IC further includes a second mixed signal interface block coupled to a second pad in the plurality of pads, where the second mixed signal interface block is adapted to receive and track a first input signal from the circuit external to the IC in a first mode of operation of the IC. The second mixed signal interface block is further adapted to generate, in response to the second trigger signal, a first output signal based on the first input signal and to provide the first output signal to a digital core of the IC in a second mode of operation of the IC, where the power consumption of the IC is lower in the first mode of operation than in the second mode of operation.
1. An integrated circuit (IC), comprising:
a plurality of pads adapted to communicate signals with a circuit external to the IC;
a first mixed signal interface block coupled to a first pad in the plurality of pads, the first mixed signal interface block adapted to receive a first trigger signal from the circuit external to the IC and to provide a second trigger signal; and
a second mixed signal interface block coupled to a second pad in the plurality of pads, the second mixed signal interface block adapted to receive and track a first input signal from the circuit external to the IC in a first mode of operation of the IC, and to generate, in response to the second trigger signal, a first output signal based on the first input signal and to provide the first output signal to a digital core of the IC in a second mode of operation of the IC,
wherein a power consumption of the IC is lower in the first mode of operation than in the second mode of operation.
2. The IC according to claim 1 , wherein the first mode of operation of the IC comprises a low power mode of operation.
3. The IC according to claim 2 , wherein the second mode of operation of the IC comprises a normal mode of operation.
4. The IC according to claim 1 , wherein in the first mode of operation of the IC, the second mixed signal interface block is further adapted to track the first input signal.
5. The IC according to claim 4 , wherein in the second mode of operation of the IC, the second mixed signal interface block is further adapted to generate a first digital signal by analog-to-digital conversion of the first input signal and to provide the first digital signal to the digital core of the IC.
6. The IC according to claim 1 , further comprising a third mixed signal interface block coupled to a third pad in the plurality of pads, the third mixed signal interface block adapted to receive and track a second input signal from the circuit external to the IC in the first mode of operation of the IC, and to generate, in response to the second trigger signal, a second output signal based on the second input signal and to provide the second output signal to the digital core of the IC in the second mode of operation of the IC.
7. The IC according to claim 6 , wherein in the first mode of operation of the IC, the third mixed signal interface block is further adapted to track the second input signal.
8. The IC according to claim 7 , wherein in the second mode of operation of the IC, the third mixed signal interface block is further adapted to generate a second digital signal by analog-to-digital conversion of the second input signal and to provide the second digital signal to the digital core of the IC.
9. The IC according to claim 6 , further comprising a fourth mixed signal interface block coupled to a fourth pad in the plurality of pads, the third mixed signal interface block adapted to generate, in response to the second trigger signal, a third output signal based on a digital signal from the digital core of the IC, and to provide the third output signal to the circuit external to the IC in the second mode of operation of the IC.
10. The IC according to claim 9 , wherein the fourth mixed signal interface block is further adapted to generate the third output signal by digital-to-analog conversion of the digital signal from the digital core of the IC.
11. The IC according to claim 1 , wherein the first mixed signal interface block provides the second trigger signal asynchronously with respect to a clock signal of the digital core of the IC.
12. The IC according to claim 11 , wherein the second mixed signal interface block generates the first output signal asynchronously with respect to the clock signal of the digital core of the IC.
13. A mixed signal integrated circuit (IC), comprising:
a digital core comprising microcontroller (MCU) circuitry;
a plurality of pads adapted to communicate signals with a circuit external to the IC;
a first mixed signal interface block coupled to a first pad in the plurality of pads, the first mixed signal interface block adapted to receive a first trigger signal from the circuit external to the IC and to provide a second trigger signal;
a trigger circuit adapted to, in response to the second trigger signal, generate a third trigger signal and to generate an interrupt signal and provide the interrupt trigger signal to the digital core of the mixed signal IC; and
a second mixed signal interface block coupled to a second pad in the plurality of pads, the second mixed signal interface block adapted to receive and track a first analog signal from the circuit external to the mixed signal IC in a first mode of operation of the mixed signal IC, and in response to the third trigger signal, convert the first analog signal to a first digital signal and to provide the first digital signal to the digital core of the mixed signal IC in a second mode of operation of the mixed signal IC.
14. The mixed signal IC according to claim 13 , wherein the first mode of operation of the mixed signal IC comprises a low power mode of operation, and the second mode of operation of the mixed signal IC comprises a normal mode of operation.
15. The mixed signal IC according to claim 14 , wherein the first mixed signal interface block is further adapted to provide the second trigger signal during the first mode of operation, and wherein the trigger circuit is further adapted to provide the third trigger signal and the interrupt signal during the first mode of operation of the mixed signal IC.
16. The mixed signal IC according to claim 15 , wherein the digital core of the mixed signal IC is adapted to exit the first mode of operation and enter the second mode of operation in response to the interrupt signal.
17. The mixed signal IC according to claim 15 , wherein the second and third trigger signals and the interrupt signal are generated asynchronously with respect to a clock signal of the mixed signal IC.
18. A method of processing signals using a mixed signal integrated circuit (IC), the method comprising:
operating the mixed signal IC in a first mode of operation;
tracking in a first mixed signal interface block, coupled to a first pad of the mixed signal IC, a first input signal from the circuitry external to the mixed signal IC in the first mode of operation;
using a second mixed signal interface block coupled to a second pad of the mixed signal IC to receive a first trigger signal from the circuitry external to the mixed signal IC and to generate a second trigger signal;
operating the mixed signal IC in a second mode of operation in response to the second trigger signal, wherein a power consumption of the mixed signal IC is lower in the first mode of operation than in the second mode of operation; and
converting, in the second mode of operation, the first input signal to a digital signal by performing analog-to-digital conversion in the first mixed signal interface block.
19. The method according to claim 18 , wherein operating the mixed signal IC in the first mode of operation further comprises operating circuitry in the mixed signal IC, including a digital core of the mixed signal IC, in a lower power mode of operation.
20. The method according to claim 19 , wherein operating the mixed signal IC in the second mode of operation in response to the second trigger signal, further comprises operating circuitry in the mixed signal IC, including the digital core of the mixed signal IC, in a normal mode of operation.