Tiered schematic-driven layout synchronization in electronic design automation

1. A computer-implemented method for facilitating creation of a layout from a schematic in an electronic design automation (EDA) application, comprising:

performing a tiered comparison of the schematic and the layout, which involves:

performing a first tier comparison that compares labels in the schematic and the layout;

in response to detecting no mismatches during the first tier comparison, not performing a second tier comparison that compares first-level connectivity in the schematic and the layout; and

in response to detecting a mismatch during the first tier comparison, performing the second tier comparison;

providing a result of the tiered comparison to a user of the EDA application; and

enabling repairs of mismatches in the result by the user through a graphical user interface (GUI) associated with the EDA application.

2. The computer-implemented method of claim 1 , further comprising:

automatically generating a portion of the layout using the schematic.

3. The computer-implemented method of claim 2 , wherein automatically generating the portion of the layout involves:

automatically placing a component in the layout based at least on an optimization goal associated with the layout.

4. The computer-implemented method of claim 1 , wherein enabling repairs of mismatches by the user through the GUI involves at least one of:

enabling automatic correction of the mismatches through the GUI; and

marking the mismatches in the layout.

5. The computer-implemented method of claim 1 , wherein the first tier comparison involves:

comparing components in the schematic and the layout using at least one of a component name, a terminal set, and a signal net.

6. The computer-implemented method of claim 1 , wherein the second tier comparison involves at least one of:

generating a source graph from the schematic and a target graph from the layout;

comparing node counts and edge counts from the source graph and the target graph;

comparing edge-incidence counts from the source graph and the target graph; and

using shared cell masters and the edge-incidence counts to match cell instances in the schematic and the layout.

7. The method of claim 1 , wherein performing the tiered comparison of the schematic and the layout further involves, in response to detecting a mismatch during the second tier comparison, performing a third tier comparison that determines a graph isomorphism between the schematic and the layout.

8. The computer-implemented method of claim 1 , wherein the tiered comparison is a full comparison or an incremental comparison.

9. A system for facilitating creation of a layout from a schematic in an electronic design automation (EDA) application, comprising:

a comparison apparatus configured to perform a tiered comparison of the schematic and the layout by:

performing a first tier comparison that compares labels in the schematic and the layout;

in response to detecting no mismatches during the first tier comparison, not performing a second tier comparison that compares first-level connectivity in the schematic and the layout; and

in response to detecting a mismatch during the first tier comparison, performing the second tier comparison;

a GUI configured to:

provide a result of the tiered comparison to a user of the EDA application; and

enable repairs of mismatches in the result by the user.

10. The system of claim 9 , further comprising:

a layout-editing apparatus configured to automatically generate a portion of the layout using the schematic.

11. The system of claim 10 , wherein automatically generating the portion of the layout involves:

automatically placing a component in the layout based at least on an optimization goal associated with the layout.

12. The system of claim 9 , wherein enabling repairs of mismatches by the user through the GUI involves at least one of:

enabling automatic correction of the mismatches through the GUI; and

marking the mismatches in the layout.

13. The system of claim 9 , wherein the first tier comparison involves:

comparing components in the schematic and the layout using at least one of a component name, a terminal set, and a signal net.

14. The system of claim 9 , wherein the second tier comparison involves at least one of:

generating a source graph from the schematic and a target graph from the layout;

comparing node counts and edge counts from the source graph and the target graph;

comparing edge-incidence counts from the source graph and the target graph; and

using shared cell masters and the edge-incidence counts to match cell instances in the schematic and the layout.

15. The system of claim 9 , wherein the tiered comparison is a full comparison or an incremental comparison.

16. The system of claim 9 , wherein the comparison apparatus is further configured to perform a third tier comparison that determines a graph isomorphism between the schematic and the layout in response to detecting a mismatch during the second tier comparison.

17. A non-transitory computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for facilitating creation of a layout from a schematic in an electronic design automation (EDA) application, the method comprising:

performing a tiered comparison of the schematic and the layout, which involves:

performing a first tier comparison that compares labels in the schematic and the layout;

in response to detecting no mismatches during the first tier comparison, not performing a second tier comparison that compares first-level connectivity in the schematic and the layout; and

in response to detecting a mismatch during the first tier comparison, performing the second tier comparison;

providing a result of the tiered comparison to a user of the EDA application; and

enabling repairs of mismatches in the result by the user through a graphical user interface (GUI) associated with the EDA application.

18. The non-transitory computer-readable storage medium of claim 17 , the method further comprising:

automatically generating a portion of the layout using the schematic.

19. The non-transitory computer-readable storage medium of claim 18 , wherein automatically generating the portion of the layout involves:

automatically placing a component in the layout based at least on an optimization goal associated with the layout.

20. The non-transitory computer-readable storage medium of claim 17 , wherein enabling repairs of mismatches by the user through the GUI involves at least one of:

enabling automatic correction of the mismatches through the GUI; and

marking the mismatches in the layout.

21. The non-transitory computer-readable storage medium of claim 17 , wherein the first tier comparison involves:

comparing components in the schematic and the layout using at least one of a component name, a terminal set, and a signal net.

22. The non-transitory computer-readable storage medium of claim 17 , wherein the second tier comparison involves at least one of:

generating a source graph from the schematic and a target graph from the layout;

comparing node counts and edge counts from the source graph and the target graph;

comparing edge-incidence counts from the source graph and the target graph; and

using shared cell masters and the edge-incidence counts to match cell instances in the schematic and the layout.

23. The non-transitory computer-readable storage medium of claim 17 , wherein the tiered comparison is a full comparison or an incremental comparison.

24. The non-transitory computer-readable storage medium of claim 17 , wherein performing the tiered comparison of the schematic and the layout further involves, in response to detecting a mismatch during the second tier comparison, performing a third tier comparison that determines a graph isomorphism between the schematic and the layout.