Method, system, and apparatus for efficiently driving a transistor with a booster in voltage supply
View Patent ↗A method, system, and apparatus for driving a Silicon Carbide (SiC) Junction Field Effect Transistor (JFET) are provided. A boosting capacitor is used in combination with two drivers to efficiently provide a boosting current to the SiC JFET and then a holding current to the SiC JFET. The boosting capacitor, upon discharge, creates the boosting current and once discharged the holding current is provided by one of the first and second drivers.
1. A driver circuit, comprising:
a first driver configured to provide a first output voltage and first output current to a gate of a Junction Field-Effect Transistor (JFET) for a first amount of time;
a second driver configured to provide a second output voltage to a boosting capacitor, wherein the boosting capacitor is configured to boost and activate the JFET upon discharge by providing a second output current to the gate of the JFET for a second amount of time that is less than the first amount of time.
2. The driver circuit of claim 1 , wherein the JFET is a Silicon Carbide (SiC) JFET that comprises a drain and a source and wherein the drain is configured to provide a high current output while in an ON state.
3. The driver circuit of claim 2 , wherein the gate of the SiC JFET is connected to the first driver via a gate resistor and wherein the SiC JFET is configured to be in an ON state after the boosting capacitor has discharged until the first driver is turned off.
4. The driver circuit of claim 1 , wherein the first driver comprises at least one transistor having a source, gate, and at least one of a drain and collector and wherein the boosting capacitor is connected between an output of the second driver and at least one terminal of the at least one transistor.
5. The driver circuit of claim 4 , wherein the at least one transistor comprises at least one of a P-type MOSFET (PMOS) and an NPN Bipolar Junction Transistor (BJT).
6. The driver circuit of claim 1 , wherein the first driver comprises a first P-type MOSFET (PMOS) and a first N-type MOSFET (NMOS) and wherein the second driver comprises a second PMOS and a second NMOS.
7. The driver circuit of claim 6 , wherein a drain of the first PMOS is connected to a drain of the first NMOS at an output of the first driver, wherein a drain of the second PMOS is connected to a drain of the second NMOS at an output of the second driver, wherein the output of the second driver is connected to a first side of the boosting capacitor, and wherein a second side of the boosting capacitor is connected to a source of the first PMOS.
8. The driver circuit of claim 7 , wherein a source of the first NMOS and a source of the second NMOS are connected to a common voltage and wherein both the first PMOS and the second PMOS are turned on in response to a single input, S 1 , exceeding a predetermined logic supply level.
9. The driver circuit of claim 1 , further comprising:
driver logic configured to simultaneously control the first and second drivers with only a single input.
10. The driver circuit of claim 9 , wherein the driver logic comprises at least one of firmware, an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), an analog circuit element, and a digital circuit element.
11. The driver circuit of claim 1 , wherein the first output current is provided to a plurality of JFETs connected in parallel.
12. The driver circuit of claim 11 , further comprising at least one current buffer provided between the plurality of JFETs and the output of the first driver.
13. The driver circuit of claim 12 , wherein the at least one current buffer comprises a first Bipolar Junction Transistor (BJT) and a second BJT.
14. The driver circuit of claim 13 , wherein the first BJT directly receives an output from the first driver and wherein the second BJT directly receives an output from the second driver.
15. The driver circuit of claim 14 , wherein the first BJT shares a supply source with the first driver and wherein the second BJT shares a supply source with the second driver.
16. The driver circuit of claim 13 , wherein a gate resistor is provided between an output of the first BJT and the boosting capacitor.
17. The driver circuit of claim 9 , wherein the driver logic receives an input from a light detector and wherein the input received from the light detector controls operations of the driver logic.
18. The driver circuit of claim 17 , wherein the light detector comprises at least one of a photodiode, a photoresistor, a photovoltaic cell, a phototransistor, and an Integrated Circuit (IC) chip comprising one or more photodetector components.
19. The driver circuit of claim 1 , further comprising:
a diode provided between the boosting capacitor and a supply voltage, wherein the diode is configured to block the supply voltage from discharge of the boosting capacitor.
20. The driver circuit of claim 19 , further comprising:
a holding resistor provided between the boosting capacitor and diode, wherein the holding resistor along with the boosting capacitor set current provided by the supply voltage to the first driver.