IP Library Granted Patent US 8,782,579
Granted Patent B2
US 8,782,579 · App. 13/280,961 · Granted Jul 15, 2014

Connection verification method, recording medium thereof, and connection verification apparatus

Inventors: Satoshi Matsubara (Kawasaki, JP); Akira Kurokawa (Yokohama, JP)
Assignees: Fujitsu Limited; Fujitsu Semiconductor Limited
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,782,579
App. No.
13/280,961
Granted
Jul 15, 2014
Kind
B2
Abstract

A connection verification method is disclosed. A computer verifies a connection between a first node and a second node by starting from the first node in a designed integrated circuit, based on connection information stored in a storage part. The computer detects whether a module connected to the second node is a predetermined module predetermined module having a logic condition therein, based on connection relationship logic information stored in the storage part. The computer conducts a connection verification starting the module to verify a connection between the module and a third node when the module is the predetermined module.

Claims (40)

1. A connection verification method performed in a computer, the method comprising:

verifying, by the computer, a connection between a first node and a second node by starting from the first node in a designed integrated circuit in a logical path search, based on connection information stored in a storage part;

detecting, by the computer, whether a module connected to the second node is a predetermined module which has a logic condition for continuing the logical path search and is set as a logical path origin;

conducting, by the computer, a connection verification starting the module to verify a connection between the module and a third node, by setting the module as the logical path origin when the module is the predetermined module;

setting, by the computer, a loop detection flag for the module when a passage flag is set for the module;

detecting, by the computer, the module where the loop detection flag is not set in a group of circuits which operate by the same power source; and

determining, by the computer, a path from the module to a next node to be a power domain boundary, when the next node to be connected by starting from the module is a node other than an external terminal.

2. The connection verification method as claimed in claim 1 , wherein when the module is not the predetermined module, the connection verification is terminated at the second node.

3. The connection verification method as claimed in claim 1 , wherein the predetermined module does not require a logic condition for the logic connection.

4. The connection verification method as claimed in claim 1 , wherein the predetermined module requires a logic condition for the logic connection, and

the conducting the connection verification includes:

detecting, by the computer, whether an input terminal and an output terminal of the module are connected based on the logic condition; and

conducting, by the computer, the connection verification starting from the module to the third node when the input terminal and the output terminal are connected.

5. The connection verification method as claimed in claim 1 , further comprising:

detecting, by the computer, the module for which the loop detection flag is set; and

extracting, by the computer, loop paths in one or more logical paths formed by passing the module.

6. The connection verification method as claimed in claim 5 , wherein a recognized loop path recognized by a specification is excluded from the loop paths being extracted.

7. The connection verification method as claimed in claim 6 , wherein loop paths excluding the recognized loop path include a negative feedback loop.

8. The connection verification method as claimed in claim 1 , wherein the passage flag is set for the module, when the connection verification starting from the module to the third node is conducted.

9. The connection verification method as claimed in claim 1 , wherein an inversion flag is set for the module, when the connection verification starting from the module to the third node is conducted and an input signal is inversed by the module.

10. The connection verification method as claimed in claim 1 , further comprising:

detecting, by the computer, the module where the loop detection flag is not set in a group of circuits which operate by the same clock; and

determining, by the computer, a path from the module to a next node to be a clock domain boundary, when the next node to be connected by starting from the module is a node other than an external terminal.

11. A non-transitory computer-readable recording medium recorded with a program which, when executed by a computer, causes the computer to perform a connection verification process comprising:

verifying a connection between a first node and a second node by starting from the first node in a designed integrated circuit in a logical path search, based on connection information stored in a storage part;

detecting whether a module connected to the second node is a predetermined module which has a logic condition for continuing the logical path search and is set as a logical path origin;

conducting a connection verification starting the module to verify a connection between the module and a third node, by setting the module as the logical path origin when the module is the predetermined module;

setting a loop detection flag for the module when a passage flag is set for the module;

detecting the module where the loop detection flag is not set in a group of circuits which operate by the same power source; and

determining a path from the module to a next node to be a power domain boundary, when the next node to be connected by starting from the module is a node other than an external terminal.

12. A connection verification apparatus comprising:

a processor; and

a storage part;

wherein the processor performs a process including:

verifying a connection between a first node and a second node by starting from the first node in a designed integrated circuit in a logical path search, based on connection information stored in the storage part;

detecting whether a module connected to the second node is a predetermined module which has a logic condition for continuing the logical path search and is set as a logical path origin;

conducting a connection verification starting the module to verify a connection between the module and a third node, by setting the module as the logical path origin when the module is the predetermined module;

setting a loop detection flag for the module when a passage flag is set for the module;

detecting the module where the loop detection flag is not set in a group of circuits which operate by the same power source; and

determining a path from the module to a next node to be a power domain boundary, when the next node to be connected by starting from the module is a node other than an external terminal.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2015
From: FUJITSU SEMICONDUCTOR LIMITED
To: SOCIONEXT INC.
Reel/Frame 035498/0324 →
CORRECTIVE ASSIGNMENT TO CORRECT THE SECOND ASSIGNEE PREVIOUSLY RECORDED ON REEL 027348 FRAME 382. ASSIGNOR(S) HEREBY CONFIRMS THE SECOND ASSIGNEE IS: FUJITSU SEMICONDUCTOR LIMITED, 2-10-23 SHIN-YOKOHAMA, KOHOKU-KU, YOKOHAMA-SHI, KANAGAWA, 222-0033 JAPAN. Recorded Mar 14, 2014
From: MATSUBARA, SATOSHI; KUROKAWA, AKIRA
To: FUJITSU LIMITED; FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 032845/0753 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 8, 2011
From: MATSUBARA, SATOSHI; KUROKAWA, AKIRA
To: FUJITSU LIMITED
Reel/Frame 027348/0382 →
Priority Claims (1)
JP 2010-245709 · Nov 1, 2010 · national
Continuity (1)
Related Publication 20120110527A1 · May 3, 2012