Method for manufacturing a thin film transistor array panel
A method for manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention includes, forming a gate electrode, a gate insulating layer, and an oxide semiconductor layer on a substrate, first heat treating the substrate comprising the oxide semiconductor layer, forming a source electrode and a drain electrode on the oxide semiconductor layer, the source and drain electrodes facing each other, and forming a passivation layer on the source electrode and the drain electrode. The first heat treating is performed at more than 1 atmosphere and at most 50 or less atmospheres.
1. A method for manufacturing a thin film transistor array panel, comprising:
forming a gate electrode, a gate insulating layer, and an oxide semiconductor layer on a substrate;
performing a first heat treatment on the substrate comprising the oxide semiconductor layer, at a pressure in the range of more than 1 atmosphere to 50 atmospheres;
forming a source electrode and a drain electrode on the oxide semiconductor layer, after performing the first heat treatment; and
forming a passivation layer on the source electrode and the drain electrode,
wherein the first heat treatment does not change a crystalline structure of the oxide semiconductor layer.
2. The method of claim 1 , wherein the first heat treatment is performed at a temperature of at most 400° C.
3. The method of claim 1 , further comprising forming a pixel electrode on the passivation layer.
4. The method of claim 1 , wherein the oxide semiconductor comprises one of tantalum-indium-zinc oxide, indium-zinc-tin oxide, and indium-gallium-zinc oxide.
5. The method of claim 2 , wherein the first heat treatment is performed for at least 30 minutes.
6. The method of claim 5 , further comprising performing a second heat treatment after forming the passivation layer.
7. The method of claim 6 , wherein the second heat treatment is performed at a temperature of 400° C. or less.
8. The method of claim 7 , wherein the second heat treatment is performed at 1 atmosphere.
9. The method of claim 8 , wherein the first heat treatment is performed at a pressure in the range of 5 atmospheres to 30 atmospheres.
10. The method of claim 3 , further comprising performing a heat treatment on the substrate comprising the pixel electrode.
11. A method for manufacturing a thin film transistor array panel, comprising:
forming a gate electrode, a gate insulating layer, and an oxide semiconductor layer on a substrate;
forming an etch stopper on the oxide semiconductor layer;
performing a first heat treatment on the substrate comprising the etch stopper, at a pressure in the range of more than 1 atmosphere to 50 atmospheres;
forming a source electrode and a drain electrode on the oxide semiconductor layer, the source and drain electrodes contacting opposing portions of the etch stopper; and
forming a passivation layer on the substrate comprising the source electrode and the drain electrode.
12. The method of claim 11 , wherein the first heat treatment is performed at a temperature of 400° C. or less.
13. The method of claim 12 , wherein the first heat treatment is performed for at least 30 minutes.
14. The method of claim 13 , further comprising performing a second heat treatment on the substrate comprising the passivation layer.
15. The method of claim 14 , wherein the second heat treatment is performed at a temperature of 400° C. or less.
16. The method of claim 15 , wherein the second heat treatment is performed at 1 atmosphere.
17. The method of claim 16 , wherein the first heat treatment is performed at a pressure in the range of 5 atmospheres to 30 atmospheres.