Semiconductor device and method of controlling semiconductor device

1. A semiconductor device comprising:

a memory cell having a variable resistance device; and

a control unit that controls a voltage applied to the memory cell,

wherein the variable resistance device includes

a first electrode containing a first metal material,

a second electrode containing a second metal material, and

an insulating film, provided between the first electrode and the second electrode, that contains a third metal material and oxygen,

the first metal material has a normalized oxide formation energy higher than that of the second metal material, and

the control unit applies a positive voltage to the second electrode at the time of an operation of increasing a resistance value of the insulating film and an operation of decreasing the resistance value thereof, and applies a positive voltage to the first electrode at the time of an operation of reading out the resistance value of the insulating film.

2. The semiconductor device according to claim 1 , wherein when normalized oxide formation energies of the first metal material, the second metal material, and the third metal material are defined as ΔH f1 , ΔH f2 , and ΔH f3 , respectively, relationships of ΔH f1 ≧ΔH f3 /7+220 (kJ/mol) and ΔH f2 ≦ΔH f3 /7+100 (kJ/mol) are satisfied.

3. The semiconductor device according to claim 1 , wherein the variable resistance device is a unipolar type.

4. The semiconductor device according to claim 1 , wherein the insulating film is formed of Ta 2 O 5 , a laminated film of Ta 2 O 5 and TiO 2 , ZrO 2 , a laminated film of ZrO 2 and Ta 2 O 5 , NiO, SrTiO 3 , SrRuO 3 , Al 2 O 3 , La 2 O 3 , HfO 2 , Y 2 O 3 or V 2 O 5 .

5. The semiconductor device according to claim 4 , wherein the insulating film is formed of Ta 2 O 5 , and

when the normalized oxide formation energies of the first metal material and the second metal material are defined as ΔH f1 and ΔH f2 , respectively, relationships of ΔH f1 >280 (kJ/mol) and ΔH f2 <160 (kJ/mol) are satisfied.

6. The semiconductor device according to claim 1 , wherein the first electrode is formed of W, Al, TiN, Ti, Ta, TaN, Hf, HfN, Zr, ZrN, or an alloy thereof.

7. The semiconductor device according to claim 1 , wherein the second electrode is formed of Ru, RuO 2 , Pt, Ir, Rh, Pd, Cu, or an alloy thereof.

8. The semiconductor device according to claim 1 , wherein the positive voltage applied to the first electrode at the time of the operation of reading out the resistance value of the insulating film is 0.8 V or higher.

9. The semiconductor device according to claim 1 , further comprising a first interfacial layer, provided between the first electrode and the insulating film,

wherein a stoichimetric composition of the first interfacial layer is expressed by M x O y (M: metal element), and the interfacial layer has a composition ratio of oxygen to a metal element M which is smaller than y/x.

10. The semiconductor device according to claim 9 , wherein the first interfacial layer has Ta 2 O 5 as a stoichiometric composition.

11. The semiconductor device according to claim 1 , further comprising a second interfacial layer provided between the first electrode and the insulating film, formed of a metal oxide of which an electronic density of states at a conduction band minimum is equal to or smaller than an electronic density of states at a valence band maximum.

12. The semiconductor device according to claim 11 , wherein the second interfacial layer is a layer formed of MgO, CaO, Al 2 O 3 , Ga 2 O 3 , or SiO 2 , or a layer including at least one of MgO, CaO, Al 2 O 3 , Ga 2 O 3 , and SiO 2 .

13. The semiconductor device according to claim 1 , further comprising a third interfacial layer, provided between the first electrode and the insulating film, which is formed of an oxide of a metal material having a valence lower than that of the third metal material constituting the insulating film.

14. The semiconductor device according to claim 13 , wherein the third metal material is Al, Y or La, and

the third interfacial layer is a layer formed of MgO or CaO, or a layer including at least one of MgO and CaO.

15. The semiconductor device according to claim 13 , wherein the third metal material is Ti, Zr or Hf, and

the third interfacial layer is a layer formed of MgO, CaO, Al 2 O 3 , Y 2 O 3 or La 2 O 3 , or a layer including at least one of MgO, CaO, Al 2 O 3 , Y 2 O 3 and La 2 O 3 .

16. The semiconductor device according to claim 13 , wherein the third metal material is V or Ta, and

the third interfacial layer is a layer formed of MgO, CaO, Al 2 O 3 , Y 2 O 3 , La 2 O 3 , TiO 2 , ZrO 2 , or HfO 2 , or a layer including at least one of MgO, CaO, Al 2 O 3 , Y 2 O 3 , La 2 O 3 , TiO 2 , ZrO 2 , and HfO 2 .

17. The semiconductor device according to claim 1 , further comprising a fourth interfacial layer, provided between the first electrode and the insulating film, which has an impurity functioning as a donor.

18. The semiconductor device according to claim 1 , wherein the memory cell has a selection transistor, and

the control unit applies a positive voltage to the first electrode side, and then stops the application of a positive voltage to the first electrode side, and applies a positive voltage to the selection transistor, at the time of the operation of reading out the resistance value of the insulating film.

19. The semiconductor device according to claim 18 , wherein the first electrode is connected to the selection transistor.

20. The semiconductor device according to claim 1 , further comprising an interconnect provided on the memory cell,

wherein the memory cell has a selection transistor, and

one of the first electrode and the second electrode is connected to the interconnect, and the other one is connected to a source/drain region of the selection transistor.

21. The semiconductor device according to claim 20 , wherein the other one of the first electrode and the second electrode is constituted by a first contact that connects the insulating film and the source/drain region.

22. The semiconductor device according to claim 20 , further comprising a silicide layer formed in a surface of the source/drain region,

wherein the other one of the first electrode and the second electrode is formed of the silicide layer.

23. The semiconductor device according to claim 20 , further comprising the plurality of memory cells arranged in an array.

24. The semiconductor device according to claim 23 , wherein two adjacent memory cells are configured such that one of the source/drain regions which is not connected to the variable resistance device is formed integrally therewith, and the source/drain region integrally formed is connected to a bit line through one bit contact.

25. The semiconductor device according to claim 23 , further comprising a device isolation electrode located between the selection transistor included in one memory cell and the selection transistor included in another memory cell adjacent to the one memory cell.

26. The semiconductor device according to claim 23 , wherein the two adjacent memory cells connected to the same bit line are configured such that the one of the first electrode and the second electrode is formed integrally therewith, the other is separated therefrom, and the one of the first electrode and the second electrode which is formed integrally therewith is connected to a plate line through one plate contact.

27. The semiconductor device according to claim 23 , wherein the two adjacent memory cells connected to bit lines different from each other are configured such that the one of the first electrode and the second electrode is formed integrally therewith, the other is separated therefrom, and the one of the first electrode and the second electrode which is formed integrally therewith is connected to a plate line through one plate contact.

28. The semiconductor device according to claim 23 , wherein the plurality of memory cells which is connected to bit lines different from each other and is arranged in one direction is configured such that the one of the first electrode and the second electrode is formed integrally therewith, and the other is separated therefrom.

29. The semiconductor device according to claim 20 , wherein the one of the first electrode and the second electrode is constituted by a second contact that connects the interconnect and the insulating film.

30. The semiconductor device according to claim 20 , wherein the one of the first electrode and the second electrode is constituted by the interconnect.

31. A method of controlling a semiconductor device including a first electrode containing a first metal material, a second electrode containing a second metal material, and an insulating film, provided between the first electrode and the second electrode, that contains a third metal material and oxygen, the first metal material having a normalized oxide formation energy higher than that of the second metal material, the method comprising:

applying a positive voltage to the second electrode at the time of an operation of increasing a resistance value of the insulating film and an operation of decreasing the resistance value thereof, and applying a positive voltage to the first electrode at the time of an operation of reading out the resistance value of the insulating film.