Clock data recovery circuit
A clock and data recovery (CDR) circuit having a phase locked module and a frequency locked module is provided. A phase detector of the phase locked module compares a phase of an input data stream with a phase of a data-recovery clock to output an adjusting signal. The frequency locked module performs a first-order integration process and a second-order integration process on the adjusting signal to generate a first integration error and a frequency control signal. The phase locked module generates a phase control signal according to the first integration error and the adjusting signal. An oscillation circuit of the frequency locked module generates at least one reference clock according to the frequency control signal. A phase converter of the phase locked module outputs the data-recovery clock to the phase detector according to the phase control signal and the reference clock.
1. A clock and data recovery circuit, comprising:
a phase detector, comparing a phase of an input data stream with a phase of a data-recovery clock to output an adjusting signal;
a first integration module, coupled to the phase detector, and performing an integration process on the adjusting signal to output a first integration phase error;
an operation unit, coupled to the first integration module, and operating the first integration phase error and the adjusting signal to obtain an operation value;
a second integration module, coupled to the operation unit, and performing an integration process on the operation value to output a phase control signal;
a third integration module, coupled to the first integration module, and performing an integration process on the first integration phase error to output a frequency control signal;
an oscillation circuit, coupled to the third integration module, and generating at least one reference clock according to the frequency control signal; and
a phase converter, coupled to the oscillation circuit, the second integration module and the phase detector, and outputting the data-recovery clock to the phase detector according to the phase control signal and the reference clock.
2. The clock and data recovery circuit as claimed in claim 1 , further comprising an amplifier coupled between the phase detector and the operation unit for multiplying the adjusting signal by a predetermined ratio, so as to output the adjusting signal multiplied with the predetermined ratio to the operation unit.
3. The clock and data recovery circuit as claimed in claim 1 , wherein at least one integration module of the first integration module, the second integration module and the third integration module comprises an amplifier and an integrator for respectively performing a gain process and an integration process on an input of the at least one integration module.
4. The clock and data recovery circuit as claimed in claim 1 , wherein at least one integration module of the first integration module, the second integration module and the third integration module comprises an integrator for performing an integration process on an input of the at least one integration module.
5. The clock and data recovery circuit as claimed in claim 1 , further comprising a frequency divider coupled to the oscillation circuit for dividing a frequency of the reference clock to generate a system clock.
6. The clock and data recovery circuit as claimed in claim 1 , wherein the phase detector samples the input data stream according to the data-recovery clock to output a data-recovery stream.
7. The clock and data recovery circuit as claimed in claim 1 , wherein the input data stream is a serial data stream.
8. The clock and data recovery circuit as claimed in claim 1 , wherein the oscillation circuit generates a plurality of reference clocks with a same frequency and different phases according to the frequency control signal, and the phase converter is a phase selector for selecting the data-recovery clock from the reference clocks according to the phase control signal.
9. The clock and data recovery circuit as claimed in claim 1 , wherein the oscillation circuit generates a plurality of reference clocks with a same frequency and different phases according to the frequency control signal, and the phase converter is a phase interpolator for performing a phase interpolation process on the reference clocks according to the phase control signal, so as to output the data-recovery clock.
10. A clock and data recovery circuit, comprising:
a phase detector, comparing a phase of an input data stream with a phase of a data-recovery clock to output an adjusting signal;
a first integration module, coupled to the phase detector, and performing an integration process on the adjusting signal to output a first integration phase error;
an operation unit, coupled to the first integration module, and operating the first integration phase error and the adjusting signal to obtain an operation value;
a second integration module, coupled to the operation unit, and performing an integration process on the operation value to output a phase control signal;
an oscillation circuit, coupled to the second integration module, and generating at least one reference clock according to the first integration phase error; and
a phase converter, coupled to the oscillation circuit, the second integration module and the phase detector, and outputting the data-recovery clock to the phase detector according to the phase control signal and the reference clock.
11. The clock and data recovery circuit as claimed in claim 10 , further comprising an amplifier coupled between the phase detector and the operation unit for multiplying the adjusting signal by a predetermined ratio, so as to output the adjusting signal multiplied with the predetermined ratio to the operation unit.
12. The clock and data recovery circuit as claimed in claim 10 , wherein at least one integration module of the first integration module and the second integration module comprises an amplifier and an integrator for respectively performing a gain process and an integration process on an input of the at least one integration module.
13. The clock and data recovery circuit as claimed in claim 10 , wherein at least one integration module of the first integration module and the second integration module comprises an integrator for performing an integration process on an input of the at least one integration module.
14. The clock and data recovery circuit as claimed in claim 10 , further comprising a frequency divider coupled to the oscillation circuit for dividing a frequency of the reference clock to generate a system clock.
15. The clock and data recovery circuit as claimed in claim 10 , wherein the phase detector samples the input data stream according to the data-recovery clock to output a data-recovery stream.
16. The clock and data recovery circuit as claimed in claim 10 , wherein the input data stream is a serial data stream.
17. The clock and data recovery circuit as claimed in claim 10 , wherein the oscillation circuit generates a plurality of reference clocks with a same frequency and different phases according to the first integration phase error, and the phase converter is a phase selector for selecting the data-recovery clock from the reference clocks according to the phase control signal.
18. The clock and data recovery circuit as claimed in claim 10 , wherein the oscillation circuit generates a plurality of reference clocks with a same frequency and different phases according to the first integration phase error, and the phase converter is a phase interpolator for performing a phase interpolation process on the reference clocks according to the phase control signal, so as to output the data-recovery clock.