Semiconductor device and method of manufacturing the same
View Patent ↗The present invention discloses a semiconductor device, comprising: a substrate, a channel layer epitaxially grown in the substrate, a gate stack structure on the channel layer, gate spacers on both sides of the gate stack structure, and source/drain areas on both sides of the channel layer in the substrate, characterized in that the carrier mobility of the channel layer is higher than that of the substrate. In accordance with the semiconductor device and the method of manufacturing the same in the present invention, forming the device channel region by filling the trench with epitaxial high-mobility materials in a gate last process can enhance the carrier mobility in the channel region, thereby the device response speed is substantially improved and the device performance is greatly enhanced. Furthermore, traditional materials for a substrate are still used for the source/drain areas of the device to facilitate usage of a gate last process, thereby enhancing the performance while reducing the cost at the same time.
1. A semiconductor device, comprising: a substrate, a channel layer epitaxially grown in the substrate, a gate stack structure on the channel layer, gate spacers on both sides of the gate stack structure, and source/drain areas on both sides of the channel layer in the substrate, characterized in that the carrier mobility of the channel layer is higher than that of the substrate,
wherein on the source/drain areas and the gate spacers there is a stress layer, on which an interlayer dielectric layer (ILD) is provided, and a hard mask layer is provided on the ILD and the gate stack structure.
2. The semiconductor device according to claim 1 , wherein the channel layer comprises a buffer layer, a main channel layer and a cladding layer, the main channel layer having a carrier mobility higher than that of the substrate, the buffer layer having a lattice constant between the main channel layer and the substrate, and the cladding layer being formed of the same material as that of the substrate.
3. The semiconductor device according to claim 2 , wherein the substrate and the cladding layer comprise Si, the main channel layer comprises Ge, and the buffer layer comprises Si X Ge 1-X (0<x<1).
4. The semiconductor device according to claim 1 , wherein the gate stack structure comprises a gate liner layer, a gate insulating layer, and a gate conductive layer.
5. The semiconductor device according to claim 4 , wherein the gate liner layer comprises silicon oxide with a thickness of about 1 nm; the gate insulating layer comprises a material selected from a group consisting of silicon oxide, silicon oxynitride, and high-k materials with a thickness of about 1˜3 nm; and the gate conductive layer comprises a material selected from a group consisting of doped polysilicon, metals, metal alloy, and metal nitride or any combinations thereof.
6. The semiconductor device according to claim 1 , wherein each of the source/drain areas comprises a source/drain extension area and source/drain heavily-doped area.
7. The semiconductor device according to claim 1 , wherein the stress layer and/or the gate spacers comprise a material selected from a group consisting of SiN and diamond like amorphous carbon (DLC), and the stress layer has a thickness of about 10˜20 nm.
8. The semiconductor device according to claim 1 , wherein metal silicides are formed on the source/drain areas, and source/drain contact plugs each constituted by a block layer and a source/drain contact layer pass through the hard mask layer, the ILD and the stress layer to be in contact with the metal silicides.
9. The semiconductor device according to claim 8 , wherein the metal silicides comprise a material selected from a group consisting of PtSi, CoSi, NiSi, PtCoSi, PtNiSi, CoNiSi, and PtCoNiSi; and the block layer comprises a material selected from a group consisting of TiN and TaN with a thickness of about 1˜7 nm; and the source/drain contact layer comprises a material selected from a group consisting of metal, metal alloy, and metal nitride or the combinations thereof, wherein the metal is selected from Al, W, Ta, and Ti; and the hard mask layer comprises silicon nitride with a thickness of about 10˜50 nm.