IP Library › Granted Patent US 8,791,505
Granted Patent B2
US 8,791,505 · App. 13/788,288 · Granted Jul 29, 2014

Semiconductor device

Inventors: Yusuke Kinoshita (Kyoto, JP); Satoshi Tamura (Osaka, JP); Yoshiharu Anda (Osaka, JP); Tetsuzo Ueda (Osaka, JP)
Assignee: Panasonic Corporation
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Quick Facts
Patent No.
US 8,791,505
App. No.
13/788,288
Granted
Jul 29, 2014
Kind
B2
Abstract

A semiconductor device includes: a second nitride semiconductor layer formed on a first nitride semiconductor layer, and having a larger band gap than the first nitride semiconductor layer; and an electrode filling a recess formed in the first and second nitride semiconductor layers. The first nitride semiconductor layer has a two-dimensional electron gas layer immediately below the second nitride semiconductor layer. The electrode and the second nitride semiconductor layer are in contact with each other at a first contact interface. The electrode and a portion of the first nitride semiconductor layer corresponding to the two-dimensional electron gas layer are in contact with each other at a second contact interface connected below the first contact interface. The first contact interface is formed such that a width of the recess increases upward. The second contact interface is more steeply inclined than the first contact interface.

Claims (36)

1. A semiconductor device comprising:

a first nitride semiconductor layer;

a second nitride semiconductor layer formed on the first nitride semiconductor layer, and having a larger band gap than the first nitride semiconductor layer; and

an ohmic electrode formed to fill a recess which passes through the second nitride semiconductor layer, and is formed such that the first nitride semiconductor layer is recessed, wherein

a two-dimensional electron gas layer is formed in a portion of the first nitride semiconductor layer immediately below an interface between the first and second nitride semiconductor layers,

the ohmic electrode and the second nitride semiconductor layer are in contact with each other at least a first contact interface being a portion of a side surface of the recess,

the ohmic electrode and a portion of the first nitride semiconductor layer corresponding to the two-dimensional electron gas layer are in contact with each other at least a second contact interface being a portion of the side surface of the recess and connected below the first contact interface,

the first contact interface is formed such that a width of the recess increases from a lower surface of the second nitride semiconductor layer to an upper surface thereof, and

the second contact interface is more steeply inclined with respect to a top surface of the first nitride semiconductor layer than the first contact interface in a vicinity of a joint between the first and second contact interfaces.

2. The semiconductor device of claim 1 , wherein

the first contact interface has a plane forming a predetermined angle with respect to the top surface of the first nitride semiconductor layer, and

the second contact interface has a plane forming a steeper angle with respect to the top surface of the first nitride semiconductor layer than the predetermined angle.

3. The semiconductor device of claim 1 , wherein

at least one portion of the first contact interface is curved toward the second nitride semiconductor layer.

4. The semiconductor device of claim 1 , wherein

the second contact interface is perpendicular to the top surface of the first nitride semiconductor layer.

5. The semiconductor device of claim 1 , wherein

at least one portion of the second contact interface is curved toward the first nitride semiconductor layer.

6. The semiconductor device of claim 1 , wherein

the first contact interface is formed to extend from the upper surface of the second nitride semiconductor layer and reach the lower surface thereof.

7. The semiconductor device of claim 1 , wherein

the second nitride semiconductor layer has a layered structure made of a plurality of different nitride semiconductor layers.

8. The semiconductor device of claim 1 , wherein

the second nitride semiconductor layer includes a third nitride semiconductor layer into which conductive impurities are introduced.

9. The semiconductor device of claim 8 , wherein

the second nitride semiconductor layer includes a fourth nitride semiconductor layer into which impurities are not introduced, and

the third nitride semiconductor layer is formed on the fourth nitride semiconductor layer.

10. The semiconductor device of claim 1 , wherein

an AlN layer is formed between the first and second nitride semiconductor layers.

11. The semiconductor device of claim 1 , wherein

the ohmic electrode includes two ohmic electrodes spaced apart from each other, and

a gate electrode is formed on a region of the second nitride semiconductor layer between the two ohmic electrodes.

12. The semiconductor device of claim 1 further comprising:

an anode electrode formed at a location different from a location of the ohmic electrode, and being in Schottky contact with the second nitride semiconductor layer.

13. The semiconductor device of claim 1 , wherein

a portion of the second contact interface is below the two-dimensional electron gas layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 26, 2014
From: KINOSHITA, YUSUKE; TAMURA, SATOSHI; ANDA, YOSHIHARU; UEDA, TETSUZO
To: PANASONIC CORPORATION
Reel/Frame 032046/0344 →
Priority Claims (1)
JP 2010-243769 · Oct 29, 2010 · national
Continuity (2)
Continuation PCTJP2011002293 · Apr 19, 2011
Related Publication 20130193486A1 · Aug 1, 2013