IP Library › Granted Patent US 8,796,036
Granted Patent B2
US 8,796,036 · App. 13/173,851 · Granted Aug 5, 2014

Method and system for delta double sampling

Inventors: Keith Fife (Palo Alto, CA); Jungwook Yang (Newton, MA)
Assignee: Life Technologies Corporation
G01N27/4148Y10S436/806Y10S436/807
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Quick Facts
Patent No.
US 8,796,036
App. No.
13/173,851
Granted
Aug 5, 2014
Kind
B2
Abstract

An array of sensors arranged in matched pairs of transistors with an output formed on a first transistor and a sensor formed on the second transistor of the matched pair. The matched pairs are arranged such that the second transistor in the matched pair is read through the output of the first transistor in the matched pair. The first transistor in the matched pair is forced into the saturation (active) region to prevent interference from the second transistor on the output of the first transistor. A sample is taken of the output. The first transistor is then placed into the linear region allowing the sensor formed on the second transistor to be read through the output of the first transistor. A sample is taken from the output of the sensor reading of the second transistor. A difference is formed of the two samples.

Claims (19)

1. A method for detecting a chemical reaction, the method comprising:

inducing a chemical reaction within a well coupled to a chemically-sensitive transistor, the chemically-sensitive transistor selectively coupled to a circuit node via a select transistor;

operating the select transistor in a first mode during a first time interval of the chemical reaction, and sampling a reference signal at the circuit node;

operating the select transistor in a second mode during a second time interval of the chemical reaction, and sampling a sensor signal at the circuit node; and

normalizing the sampled sensor signal using the sampled reference signal to produce an output signal.

2. The method of claim 1 , wherein the select transistor is operating in the saturation region during the first time interval.

3. The method of claim 1 , wherein:

sampling the reference signal comprises charging a first node of a sampling capacitor to a voltage of the reference signal, and charging a second node of the sampling capacitor to a first predetermined voltage; and

sampling the sensor signal at the circuit node comprises charging the first node of the sampling capacitor to a voltage of the sensor signal, thereby inducing a voltage change at the second node of the sensor signal changes due to a difference between the voltage of the sensor signal and the voltage of the reference signal.

4. The method of claim 1 , wherein the select transistor is operating in the linear region during the second time interval.

5. The method of claim 1 , wherein the chemically-sensitive transistor is operating in the saturation region during the second time interval.

6. The method of claim 1 , wherein the chemical reaction establishes a voltage at a terminal of the chemically-sensitive transistor, and the select transistor connects the terminal of the chemically-sensitive transistor to the circuit node during the second time interval.

7. The method of claim 1 , wherein the chemical reaction is a sequencing reaction.

8. The method of claim 1 , wherein the reference signal indicates a threshold voltage of the select transistor, and the sensor signal indicates a threshold voltage of the chemically-sensitive transistor.

9. The method of claim 1 , wherein the select transistor blocks coupling of a terminal of the chemically-sensitive transistor to the circuit node during the first time interval, and connects the terminal of the chemically-sensitive transistor to the circuit node during the second time interval.

10. The method of claim 1 , wherein the select transistor selectively couples a first terminal of the chemically-sensitive transistor to the circuit node, and further comprising:

providing a bias current through the select transistor and the chemically-sensitive transistor during the first time interval and the second time interval; and

providing a bias voltage to a second terminal of the chemically-sensitive transistor.

11. The method of claim 10 , wherein the bias current and the bias voltage establish the reference signal at the circuit node during the first time interval, and establish the sensor signal at the circuit node during the second time interval.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 5, 2011
From: FIFE, KEITH; YANG, JUNGWOOK
To: LIFE TECHNOLOGIES CORPORATION
Reel/Frame 026711/0285 →
Continuity (2)
Provisional Application 61386403 · Sep 24, 2010
Related Publication 20120074956A1 · Mar 29, 2012