Memory power manager
Controlling access to memory includes receiving a plurality of memory access requests and assigning corresponding time values to each. The assigned time values are adjusted based upon a clock pulse and a priority access list is generated. Factors consider include missed access deadlines, closeness to missing access deadlines, and whether a page is open. The highest ranked client is then passed to a sequencer to allow the requested access. Time values may be assigned and adjusted according to client ID or client type (latency or bandwidth). A plurality of power modes of operation are defined wherein operation in a selected power mode of operation is based at least in part on the assigned or adjusted time values. The processing is performed in hardware in parallel (at the same time) by associated logic circuits.
1. A method in a memory controller for power control according to a plurality of memory power modes of operation, comprising:
generating power and resource control commands to correspond with one of the plurality of memory power modes of operation or to correspond with transitions between the plurality of memory power modes of operation;
determining to transition from a first memory power mode of operation in which read and write memory access requests are received and serviced to a second memory power mode of operation, wherein the second memory power mode of operation is a reduced memory power mode of operation in which write memory access requests are received but not serviced;
monitoring a plurality of buffers to determine if a read memory access request has been received from a memory client;
determining to change from the second memory power mode of operation to the first memory power mode of operation upon detecting that the read memory access request has been received;
if any write memory access requests are stored in the plurality of buffers, servicing the write memory access requests stored in the plurality of buffers; and
after servicing at least one of the write memory access requests, servicing the read memory access request.
2. The method of claim 1 wherein monitoring the plurality of buffers includes monitoring at least two buffers of the plurality of buffers in parallel.
3. The method of claim 1 wherein the power and resource control commands include at least one of:
power control commands for powering memory elements;
power control commands for powering buffers;
power control commands for powering drivers;
power control commands for powering phase locked loop (PLL) circuit elements; and
control commands for controlling PLL clock rates.
4. The method of claim 1 further including receiving a power mode override indication and determining to operate in one of the memory power modes of operation based on the received power mode override indication.
5. The method of claim 1 further including:
receiving a write memory access request from a first memory client;
storing the write memory access request in a buffer when in the second memory power mode of operation; and
sending an indication of a write completion to the first memory client prior to servicing the write memory access request.
6. The method of claim 5 further including:
receiving the read memory access request from one of the first memory client or a second memory client;
if any write memory access requests are stored in the buffer, servicing the write memory access requests stored in the buffer; and
after servicing at least one of the write memory access requests and based upon service timing requirements for the read memory access request, servicing the read memory access request.
7. The method of claim 5 including servicing at least a portion of the write memory access requests stored in the buffer prior to receiving the read memory access request to prevent the buffer being filled.
8. The method of claim 1 including servicing all write memory access requests stored in a buffer prior to transitioning to the second memory power mode of operation.
9. The method of claim 1 , further including logic circuitry for:
detecting that the read memory access request has been received;
generating the power and resource control commands to bring memory out of the second memory power mode of operation;
generating at least one PLL control command to receive a slower clock from a first PLL;
perform memory accesses based on the slower clock;
subsequently receive a faster clock; and
perform subsequent memory accesses based on the faster clock.
10. A memory controller with hardware based logic for power control according to a plurality of memory power modes of operation, comprising:
power mode logic for generating power and resource control commands to correspond with one of the plurality of memory power modes of operation or to correspond with transitions between the plurality of memory power modes of operation; and
wherein the memory controller:
determines to transition to a reduced memory power mode of operation in which write memory access requests are received but not serviced;
monitors a plurality of buffers to determine if a read memory access request has been received from a memory client;
determines to change from the reduced memory power mode of operation to a powered memory power mode of operation upon detecting that the read memory access request has been received;
generates at least one power and resource control command to increase power of at least one circuit block;
if any write memory access requests are stored in the plurality of buffers, service the write memory access requests stored in the plurality of buffers; and
after servicing at least one of the write memory access requests, service the read memory access request.
11. The memory controller of claim 10 wherein the memory controller further includes logic circuitry that monitors at least two of the plurality of buffers in parallel.
12. The memory controller of claim 10 wherein power mode logic generates at least one of:
power control commands for powering memory elements;
power control commands for powering buffers;
power control commands for powering drivers;
power control commands for powering for phase locked loop (PLL) circuit elements; and
control commands for controlling PLL clock rates.
13. The memory controller of claim 10 further including an interface for receiving a power mode override indication and logic for determining to operate in a memory power mode of operation based on the received power mode override indication.
14. The memory controller of claim 10 further defining logic for:
receiving a write memory access request from a first memory client;
storing the write memory access request in a buffer when in the second memory power mode of operation; and
sending an indication of a write completion to the first memory client prior to servicing the write memory access request.
15. The memory controller of claim 14 further including logic for:
receiving the read memory access request from one of the first memory client or a second memory client;
if any write memory access requests are stored in the buffer, servicing the write memory access requests stored in the buffer; and
after servicing at least one of the write memory access requests and based upon service timing requirements for the read memory access request, servicing the read memory access request.
16. The memory controller of claim 14 further including logic for servicing at least a portion of the write requests stored in the buffer prior to receiving the read memory access request to prevent the buffer being filled.
17. The memory controller of claim 10 including logic for servicing all write memory access requests stored in a buffer prior to transitioning to the reduced memory power mode of operation.
18. The memory controller of claim 10 , further including logic circuitry for:
detecting that the read memory access request has been received;
generating power and resource control commands to bring memory out of a lower the reduced memory power mode of operation;
generating at least one PLL power control command to receive a slower clock from a first PLL;
performing memory accesses based on the slower clock;
subsequently receiving a faster clock; and
performing subsequent memory accesses based on the faster clock.
19. A memory controller with hardware based logic for power control according to a plurality of memory power modes of operation, comprising:
power mode logic for generating power and resource control commands to correspond with one of the plurality of memory power modes of operation or to correspond with transitions between the plurality of memory power modes of operation, the plurality of memory power modes of operation including:
a fully operational memory power mode of operation wherein memory elements, buffers and drivers are powered up and are ready for operation and a clock is transmitted to the memory controller; and
a reduced memory power mode of operation in which write memory access requests are received but not serviced, the reduced memory power mode of operation being selected from the group consisting of:
a pre-charge mode wherein memory elements, buffers and drivers are powered up and are ready for operation but all pages of memory are closed; and
an active power down mode wherein at least one page is open but a clock is not transmitted to the memory and wherein memory elements, buffers and drivers are powered up and are ready for operation;
wherein the memory controller uses logic circuitry to monitor a plurality of buffers in parallel to determine if a read memory access request has been received from a memory client;
wherein the memory controller determines to change from the reduced memory power mode of operation to the fully operational memory power mode of operation upon detecting that the read memory access request has been received;
wherein the memory controller services at least one of the write memory access requests stored in the plurality of buffers prior to servicing the read memory access request.
20. The memory controller of claim 19 wherein the memory controller further includes logic circuitry that monitors at least two of the plurality of buffers in parallel.
21. The memory controller of claim 19 further defining logic for:
receiving a write memory access request from a first memory client;
storing the write memory access request in a buffer; and
sending an indication of a write completion to the first memory client prior to servicing the write memory access request.
22. The memory controller of claim 21 further including logic for:
receiving the read memory access request from one of the first memory client or a second memory client;
if any write memory access requests are stored in the buffer, servicing the write memory access requests stored in the buffer; and
after servicing at least one of the write memory access requests and based upon service timing requirements for the read memory access request, servicing the read memory access request.
23. The memory controller of claim 19 , further including logic circuitry for:
detecting that the read memory access request has been received;
generating memory power control commands to bring memory out of the reduced power mode of operation;
generating at least one PLL power control command to receive a slower clock from a first PLL;
performing at least one of transitioning from the reduced memory power mode of operation and servicing a write memory access based on the slower clock;
subsequently receiving a faster clock; and
subsequently operating based on the faster clock.
24. The memory controller of claim 19 wherein the memory controller:
delays servicing write memory access requests by storing the write memory access requests in a buffer until the read memory access request is received or to prevent the buffer being filled;
services write memory access requests consecutively that are associated with common pages of memory;
closes open pages of memory when new pages of the same bank are required for a pending access;
closes open pages of memory when performing a refresh; and
only opens pages of memory when needed to service an access request.