Flash memory
The present invention provides a flash memory including a memory cell, a current limiter and a program voltage generator. The memory cell is programmed in response to a program current and a program voltage. The current limiter reflects amount of the program current by a data-line signal, e.g., a data-line voltage. The program voltage generator generates and controls the program voltage in response to the data-line voltage, such that the program current can track to a constant reference current.
1. A flash memory comprising:
a p-channel metal-oxide-semiconductor (PMOS) memory cell capable of being programmed in response to a program current of a bit-line and a program voltage of a control-line terminal,
a current limiter, coupled to the bit-line, for reflecting amount of the program current by a data-line signal of a data-line terminal and receiving a reference current; and
a program voltage generator, coupled to the control-line terminal and the data-line terminal, for generating the program voltage in response to the data-line signal, such that the program current tracks to the reference current; wherein the program voltage generator is arranged to raise the program voltage in response to a rising tendency of the program current.
2. The flash memory of claim 1 , wherein the program voltage generator comprises:
a first amplifier comprising a pair of first input terminals and a first output terminal respectively coupled to the data-line terminal, a reference voltage and the control-line terminal.
3. The flash m′emory of claim 1 , wherein the current limiter comprises:
a first transistor comprising a first gate and a first drain, the first drain being coupled to the reference current; and
a second transistor comprising a second gate and a second drain respectively coupled to the first gate and the data-line terminal.
4. The flash memory of claim 3 , wherein the current limiter further comprises:
a second amplifier comprising a pair of second input terminals and a second output terminal respectively coupled to the first drain, the reference voltage and the first gate.
5. The flash memory of claim 3 , wherein the first gate is coupled to the first drain, and a voltage of the first drain is provided as the reference voltage.